VLSI design and implementation fuels the signal-processing revolution

Rabaey, Jan M.; Gass, W.; Brodersen, R.W.; Nishitani, T.; Chen, Tsuhan

doi:10.1109/79.647040

Cited by 11 publications

(2 citation statements)

References 59 publications

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“…The linker command file C6713dsk.cmd is listed in Figure 1. 16. It shows that sections such as .text reside in internal RAM (IRAM), which is mapped to the internal memory of the C6713 digital signal processor.…”

Section: Linker Command File (C6713dskcmd)mentioning

confidence: 99%

DSP Development System

Chassaing

Reay

2007

Digital Signal Processing and Applications With the TMS320C6713 and TMS320C6416 DSK

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Testing the software and hardware tools with Code Composer Studio • Use of the TMS320C6713 DSK • Programming examples to test the tools Chapter 1 introduces several tools available for digital signal processing (DSP). These tools include the popular Code Composer Studio (CCS), which provides an integrated development environment (IDE), and the DSP starter kit (DSK) with the TMS320C6713 floating-point processor onboard and complete support for input and output.Three examples illustrate both the software and hardware tools included with the DSK. It is strongly suggested that you review these three examples before proceeding to subsequent chapters.

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Section: Linker Command File (C6713dskcmd)mentioning

confidence: 99%

DSP Development System

Chassaing

Reay

2007

Digital Signal Processing and Applications With the TMS320C6713 and TMS320C6416 DSK

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“…Although the capacity of processors should double every 18 months according to Moore's Law, today's media processors can only marginally accommodate Standard Definition MPEG-2 video decoding [13], let alone more complicated video processing functions such as video encoding and enhancement. Moreover, due to the migration of functions from hardware to software, the number of algorithms that run on processors is increasing at an even faster pace than that of processor capacity [1]. Therefore, it is valid to assume that media processors will be nearly fully or fully loaded in the foreseeable future.…”

Section: Introductionmentioning

confidence: 97%

Regulated complexity scalable MPEG-2 video decoding for media processors

Chen

Zhong

Lan

et al. 2002

IEEE Trans. Circuits Syst. Video Technol.

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Video processing on programmable platforms offers significant advantages over dedicated hardware such as shorter development cycles, flexibility, and upgradability, among others. Although the emergence of powerful media processors is making video processing on programmable platforms closer to reality, practical media-processor-based systems benefit from complexity-scalable video processing algorithms that can trade off video quality against computation while ensuring real-time performance. We develop complexity-scalable MPEG-2 video decoding algorithms with both SNR quality degradation and decoding resolution reduction. We improve the decoder's complexity-quality performance by employing signal-adaptive processing in decoding blocks and picture-type-dependent processing with unequal computation resource allocation to exploit each picture type's varying impact on the overall video quality. Realizing that software video decoding operates in a dynamic environment where both the actual computation (depending on video data) and computation allocation (depending on other functions running simultaneously) vary, we develop dynamic complexity regulation techniques to ensure that the decoding complexity stays within allocation. Simulation results on complexity-scalable MPEG-2 video decoding and dynamic complexity regulation on media processors are presented.

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