VLSI Circuit Design Methodology Demystified

Xiu, Liming

doi:10.1002/9780470199114

Cited by 8 publications

(4 citation statements)

References 30 publications

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“…Library-based design is a promising solution to address this challenge as it facilitates the design reuse. Design reuse is an approach that utilizes a previously successful design in a new design project to reduce the design, verification cycle and risk [Castro-lpez et al 2006;Xiu 2007]. It also reduces design cost since the reused components have been prepared and verified [Castro-lpez et al 2006;Xiu 2007].…”

Section: Introductionmentioning

confidence: 99%

“…Design reuse is an approach that utilizes a previously successful design in a new design project to reduce the design, verification cycle and risk [Castro-lpez et al 2006;Xiu 2007]. It also reduces design cost since the reused components have been prepared and verified [Castro-lpez et al 2006;Xiu 2007]. Library based design has been studied in previous work.…”

Section: Introductionmentioning

confidence: 99%

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Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Mao

Chen

Zhang

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

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While traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used modules can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time, and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this article, we propose a library-based placement and routing flow that best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in the B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 65% on average with 17% area and 8.2% delay overhead compared with the fine-grained results of Versatile Place and Route through the reuse of module information in the library for the base architecture. For other architectures, the area increase ranges from 8.32% to 25.79%, the delay varies from − 13.66% to 19.79%, and the runtime improves by 43.31% to 77.2%.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Mao

Chen

Zhang

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

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“…Markov chains (Johnson et al, 1996), signal flow graphs (Eppinger et al, 1997) and petri-nets (Magott and Skudlarski, 1989) are other examples of graphing techniques used to analyze design processes. According to Xiu (2008):…”

Section: Introductionmentioning

confidence: 99%

Framework for Managing the Very Large Scale Integration Design Process

Hossnia¹

2012

American Journal of Applied Sciences

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Problem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based) lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as control flow and data structure. It was important to fill the gap between these two levels of description because VLSI chip manufacturing was a complex management project and providing a conceptual detailed depiction of the design process would assist in managing operations on the great number of generated artifacts. Approach: This study introduces a conceptual framework representing flows and transformations of various descriptions (e.g., circuits, technical sketches) to be used as a tracking apparatus for directing traffic during the VLSI design process. The proposed methodology views a description as an integral element of a process, called a flow system, constructed from six generic operations and designed to "handle" descriptions. It draws maps of flows of representations (called flowthings) that run through the design flow. These flowthings are created, transformed (processed), transferred, released and received by various functions along the design flow at different levels (a hierarchy). The resultant conceptual framework can be used to support designers with computer-aided tools to organize and manage chains of tasks. Results: The proposed model for managing the VLSI design process was characterized by being conceptual (no technical or implementation details) and can be uniformly applied at different levels of design and to various kinds of artifacts. The methodology is applied to describe the VLSI physical design stage that includes partitioning, floorplanning and placement, routing, compaction and extraction and verification. Conclusion: The resultant conceptual picture demonstrates a viable description method that can be adapted for different stages and used in developing systems for managing the VLSI design process.

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“…Library-based design is a promising solution to address this challenge as it facilitates the design reuse. Design reuse is an approach that utilizes a previously successful design in a new design project to reduce the design, verification cycle and risk [ClFGvRv06,Xiu07]. It also reduces design cost since the reused components have been prepared and verified [ClFGvRv06,Xiu07].…”

Section: Introductionmentioning

confidence: 99%

Design automation flow for partial run-time reconfiguration on FPGAs

Mao¹

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VLSI Circuit Design Methodology Demystified

Cited by 8 publications

References 30 publications

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Framework for Managing the Very Large Scale Integration Design Process

Design automation flow for partial run-time reconfiguration on FPGAs

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