VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

Das, Subhajit; Maity, Reshmi; Maity, N. P.

doi:10.1007/s00034-017-0609-3

Cited by 22 publications

(7 citation statements)

References 19 publications

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“…Algorithm for task-based scheduling in hybrid CPU-FPGA design states that if an application demands faster execution speed, then the level of parallel reconfiguration (Das et al, 2017) can be customised by the user through task-based scheduling on the developed HCF architecture. The pseudo code shows the skeleton view of the implementation.…”

Section: Algorithm 1: Task-based Scheduling In Hybrid Cpu-fpga Designmentioning

confidence: 99%

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Shilpa

Jawahar

2021

IJSCC

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Heterogeneous multi-core processors aim at overall performance improvement of computations for applications in the field of computing. It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor. Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics. The evaluation for all the algorithm were carried out in zybo board belonging to zynq 7010 family of all programmable system on chip FPGA board, with Xilinx vivado 2014.4 as the development software. Experimental results prove that the efficiency of the designed hybrid processor with efficient task based scheduling algorithm yields a 53% increase in the speed of execution with multi-threading and 52% performance improvement by top level pipelining.

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Section: Algorithm 1: Task-based Scheduling In Hybrid Cpu-fpga Designmentioning

confidence: 99%

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Shilpa

Jawahar

2021

IJSCC

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“…Mohanty et al [34] put forward a VLSI architecture that could insert invisible or visible watermarks into digital images in the DCT domain. Recently, Das et al [35] give a RW architecture based on difference expansion. In [34] the first low-power watermarking chip was introduced.…”

Section: B Hardware Implementationmentioning

confidence: 99%

A Digital Watermarking Encryption Technique Based on FPGA Cloud Accelerator

2020

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Digital watermarking has the properties such as invisibility and anti-aggression, so the digital watermarking technology has been widely used in copyright protection, information hiding. The watermarking technology takes into account the invisibility and robustness of the watermark by controlling the embedding intensity and position of the watermark mainly in the transformation domain. In this paper, discrete cosine transform (DCT) is adopted to transform the given image from spatial domain to frequency domain for adding watermark information. In order to meet the demands of image watermarking batch processing and cloud processing in the future, this paper optimized the DCT algorithm and the data precision, and successfully deployed the designed accelerator kernel on the FPGA cloud platform to speed up the processing of watermarking. The implementation of data processing based on cloud platform is the development trend of big data era. The cloud platform adopted in this paper is based on the OpenCL heterogeneous architecture combining CPU and FPGA. The cloud-based implementation makes digital watermarking application highly extensible, widely shareable, and more secure. The whole system implements a series of complete cloud processes including image decoding, image preprocessing, watermark embedding, and watermarked image encoding. The watermarking algorithm is accelerated by the efficient parallel computing capabilities of FPGA. It can be seen that the result of acceleration is remarkable, providing the state-of-the-art throughput of 1.676 GBps and the highest processing speed of 937 FPS for 800 × 800 sized colorimage. INDEX TERMS Cloud services, parallel operation, integer DCT, data encryption and watermarking, heterogeneous architecture.

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“…It included a wireless Wireless Fidelity (WiFi)driver, an ADC driver, an First Input First Output-Intellectual Property (FIFO-IP) core, a Flash driver, a main frequency measurement module, a first-break arrival time extraction module, a phase difference measurement module, a phase difference calibration module, a DDR3 controller, and a Zynq processor. The main frequency measurement module, the first-break arrival time extraction module, the phase difference measurement module, the phase difference calibration module, the DDR3 controller were connected to the Zynq processor through the Advanced eXtensible Interface 4.0 (AXI4) bus [28]. The Flash transmitted data to the DDR3 in the Direct Memory Access (DMA) mode.…”

Section: Hardware Implementation Of the Fpga-based Time-differencementioning

confidence: 99%

A Method of FPGA-Based Extraction of High-Precision Time-Difference Information and Implementation of Its Hardware Circuit

Yan

et al. 2019

Sensors

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The positioning technology to find shallow underground vibration sources based on a wireless sensor network is receiving great interest in the field of underground position measurements. The slow peaking and strong multi-waveform aliasing typical of the underground vibration signal result in a low extraction accuracy of the time difference and a poor source-positioning accuracy. At the same time, the transmission of large amounts of sensor data and the host computer’s slow data processing speed make locating a source a slow process. To address the above problems, this paper proposes a method for high-precision time-difference measurements in near-field blasting and a method for its hardware implementation. First, based on the broadband that is typical of blast waves, the peak frequency of the P-wave was obtained in the time–frequency domain, taking advantage of the difference in the propagation speed of the P-wave, S-wave, and the surface wave. Second, the phase difference between two sensor nodes was found by means of a spectral decomposition and a correlation measurement. Third, the phase ambiguity was eliminated using the time interval of the first break and the dynamic characteristics of the sensors. Finally, following a top-down design idea, the hardware system was designed using Field Programmable Gate Array(FPGA). Verification, using both numerical simulations and experiments, suggested that compared with generalized cross-correlation-based time-difference measurement methods, the proposed method produced a higher time-difference resolution and accuracy. Compared with the traditional host computer post-position positioning method, the proposed method was significantly quicker. It can be seen that the proposed method provides a new solution for solving high-precision and quick source-location problems, and affords a technical means for developing high-speed, real-time source-location instruments.

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VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

Cited by 22 publications

References 19 publications

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

A Digital Watermarking Encryption Technique Based on FPGA Cloud Accelerator

A Method of FPGA-Based Extraction of High-Precision Time-Difference Information and Implementation of Its Hardware Circuit

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