VLSI based Lossless ECG Compression Algorithm Implementation for Low Power Devices

Abstract

The research study presents a VLSI design of an effective electrocardiogram data encoding lossless data compression scheme to conserve disk system to minimize channel capacity. As the data compression can save disc space, reduce transfer time, and seized this ability by introducing a memory-less architecture when operating in VLSI at a high data rate. There are two components of the ECG classification technique: an adaptive frequency-domain methodology and bandwidth. An accurate and reduced VLSI compressed algorithm design has been introduced. The current VLSI architecture uses a few more procedures to substitute for the various mathematical functions to enhance performance and implemented the VLSI’s architecture to the MIT-BIH atrial fibrillation repository capable of achieving a 2.62 lossless bit compression rate. Also, the VLSI structure uses a gate count of 5.1 K.

Optimizing Real-Time ECG Data Transmission in Constrained Environments

“…It efficiently reduces the original data size by assigning short codes for most repeated characters and longer codes for less repeated characters. The majority of the previous works implement the Huffman algorithm on PC as a software compression solution, while a few contributions run the Huffman algorithm on embedded systems using FPGA and VLSI [48][49].…”