VLSI architectures for turbo codes

Abstract

A great interest has been gained in recent years by a new error-correcting code technique, known as "turbo coding," which has been proven to offer performance closer to the Shannon's limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and performance; the impact on the VLSI complexity of system parameters like the state number, number of iterations, and code rate are evaluated for the different solutions. The results of this architectural study have then been exploited for the design of a specific decoder, implementing a serial concatenation scheme with 2/3 and 3/4 codes; the designed circuit occupies 35 mm 2 , supports a 2-Mb/s data rate, and for a bit error probability of 10 06 , yields a coding gain larger than 7 dB, with ten iterations.

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues

“…Each time a received 12 See [31] and VII for an example of modelization of the hardware complexity of a turbo decoder codeword fails to be decoded, store the codeword (or information to reconstruct it, i.e., the seeds of the pseudo random generators) in a set . Stop the process when the cardinality of the set is high enough (typically around 1000).…”

“…To compensate the effect of neglecting the look-up table several strategies are possible, like scaling or offsetting the messages. These techniques are described in [31], [32] Independently from the metric used, the input-output relationships (4), (5) or (7), (8) have a complexity that grows with the size of the code. This complexity can be affordable for very simple mappings but becomes impractical for most of the mappings used as encoders.…”

Iterative Decoding of Serially Concatenated Arithmetic and Channel Codes With JPEG 2000 Applications

“…This approach requires the storage only of a section of the decoding tree of width and yields sequential decoding. The computational complexity of this sequential strategy is the same as the standard BCJR algorithm applied to a trellis with states [38], [39]. Furthermore, the construction of the decoding tree requires to perform about AC decoding steps.…”

A Mimo Receiver SOC for CDMA Applications

“…To eliminate the white Gaussian noise, maximum likelihood detection is often applied. To this end, Turbo decoding has been shown very effective in noise elimination [2,6,9].…”