VLSI architectures for recursive and multiple-window order statistic filtering

Hakami, Mona; Warter, P; Boncelet, Charles G.; Nassimi, David

doi:10.1109/ipps.1992.223030

Cited by 2 publications

(5 citation statements)

References 7 publications

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“…Processing multiple output at the same time (block processing) has many advantages, including reduction in power disspation per output and time-area complexity. 1-D block processing by merging equal size sequence was proposed in [3]. Here we propose an algorithm and its architecture of 2-D block processing for 2-D ROF by using 1-D max-min sorting network.…”

Section: Architecture Of 2-d Rank Order Filtermentioning

confidence: 99%

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Fast response 2-D rank order filter by using max-min sorting network

Lin

Kuo²

Proceedings of 3rd IEEE International Conference on Image Processing

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Based on the recently developed sorting networks, a new VLSI architecture suitable for 2-D rank order filtering is proposed. The major advantage of the proposed architecture is their fast response time and modular architecture. Generally speaking, the throughput of the proposed architecture is (N-1) times faster than using a 1-D rank order filter for 2D N x N data.The concept of block processing is also incorporated into the design to reduce the time-area complexity of the proposed architecture. Roughly speaking, the complexity is reduced to 2/3 and 1/2 compared with a rank order and median filter without using block processing architecture, respectively. A 3 x 3 median filter with block processing architecture is implemented through a 0.8,um single-poly double metal CMOS process. The simulation results are correct with a clock rate up to 91MHz.

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Section: Architecture Of 2-d Rank Order Filtermentioning

confidence: 99%

“…The architecture presented in this paper is based on the recently developed 1-D max-min sorting networks [3]. Although 1-D sorting network can be directly applied for 2-D data, doing so suffers from slow throughput.…”

Section: Introductionmentioning

confidence: 99%

Fast response 2-D rank order filter by using max-min sorting network

Lin

Kuo²

Proceedings of 3rd IEEE International Conference on Image Processing

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“…As the window slides, only one pixel element enters and leaves; the rest of the elements can be maintained in a sorted list. Based on this observation, the rank-order statistic finding problem is solved by keeping a partially sorted list and incorporating a recursive-order statistic-finding algorithm to merge in the new value [5].…”

Section: Max-min Sorting Networkmentioning

confidence: 99%

“…Processing multiple outputs at the same time (block processing) has many advantages, including reduction in power dissipation per output and time-area complexity. 1-D block processing by merging equal-size sequences was proposed in [5]. Here, we propose an algorithm and its architecture of 2-D block processing for a 2-D ROF by using a 1-D max-min sorting network.…”

Section: Architecture Of 2-d Rank-order Filtermentioning

confidence: 99%

“…Therefore, we restrict our attention here to propose a fully modular approach of a 2-D ROF with a simple and regular interconection between each modular. The architecture presented in this paper is based on the recently developed one-dimensional (1-D) max-min sorting networks [5]. Although a 1-D sorting network can be directly applied for 2-D data, doing so suffers from slow throughput.…”

Section: Introductionmentioning

confidence: 99%

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Two-dimensional rank-order filter by using max-min sorting network

Lin

Kuo

1998

IEEE Trans. Circuits Syst. Video Technol.

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Based on the recently developed sorting networks, a new VLSI architecture suitable for two-dimensional (2-D) rankorder filtering is proposed. The major advantage of the proposed architecture is their fast response time, modular architecture, and simple and regular interconnection. Generally speaking, the throughput of the proposed architecture is (N 0 1) times faster than using a one-dimensional rank-order filter for 2-D N 2 N data. The concept of block processing is also incorporated into the design to reduce the time-area complexity of the proposed architecture. Roughly speaking, the complexity is reduced to 2/3 and 1/2 compared with a rank-order and median filter without using block processing architecture, respectively. A 3 2 3 median filter with block processing architecture is implemented through a 0.8 m single-poly double-metal CMOS process. The results are correct with a clock rate up to 125 MHz.Index Terms-Block processing, max-min sorting network, rank-order filter.

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VLSI architectures for recursive and multiple-window order statistic filtering

Cited by 2 publications

References 7 publications

Fast response 2-D rank order filter by using max-min sorting network

Fast response 2-D rank order filter by using max-min sorting network

Two-dimensional rank-order filter by using max-min sorting network

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