VLIW DSP for mobile applications

Kumura, Takahiro; Ikekawa, M.; Yosbida, M.; Kuroda, I.

doi:10.1109/msp.2002.1012346

Cited by 30 publications

(14 citation statements)

References 9 publications

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“…Table 2 lists θ * and C * for two DSPs, NEC µPD77210 and NEC µPD77050 [9], which has higher performance, as well as for an embedded CPU (ARM940T [10]). Here, c 1 represents the throughput when only matching error calculations were computed.…”

Section: Estimation For Other Processorsmentioning

confidence: 99%

Optimization of decision-timing for early termination of SSDA-based block matching

Hatabu

Miyazaki

Kuroda

2003

2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698)

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This paper describes an analysis-based method for optimizing the timing of decisions regarding early termination of block matching (BM) in the application of a successive similarity detection algorithm (SSDA). Although the SSDA reduces BM computational costs, making decisions to terminate BM or not consumes additional processor cycles. Here, total costs, including cycles for decisions, are formulated through use of a decision interval, processordependent cost factors, and a function which gives probabilities of BM termination. The optimal decision interval is derived by minimizing the cost function. Experiments on MPEG-4 video coding show the proposed method facilitates comparative evaluation of the computational costs of SSDA-based BM for various processors.

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Section: Estimation For Other Processorsmentioning

confidence: 99%

Optimization of decision-timing for early termination of SSDA-based block matching

Hatabu

Miyazaki

Kuroda

2003

2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698)

Self Cite

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“…With this assump tion, we estimate the normalized power to be approximately 0.642mW/MHz, which reduces to 0.1mW/MHz at 1V sup ply. Although no Blackfin core power numbers are avail able, we can compare our estimate to a similar core from NEC the SPXK5 [37], which consumes 0.07mw/MHz in 130 nanometer technology. Given that we are using an esti mate, however, we will discuss the sensitivity of our results to tile power at the end of the results section.…”

Section: Tile Modelmentioning

confidence: 99%

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Oliver¹,

Rao²,

Sultana³

et al.

Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.

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“…HAT [15] is an effective variable-length instruction format to improve the first problem. Variable-length VLIW encoding applied on TI C64 [9] and NEC SPXK5 [16] can eliminate NOP in a packet by attaching a slot number to each instruction for runtime dispersal. Besides, an additional mark is needed for each instruction to denote the boundary of each variable-length packet (i.e.…”

Section: Instruction Encodingmentioning

confidence: 99%

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

Lin

Chen

Kuo

et al. 2007

J Sign Process Syst Sign Image

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This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1õ26.0%. The DSP has been fabricated in the UMC 0.13 mm 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 Â 3.15 mm 2 including 160 KB onchip SRAM.

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VLIW DSP for mobile applications

Cited by 30 publications

References 9 publications

Optimization of decision-timing for early termination of SSDA-based block matching

Optimization of decision-timing for early termination of SSDA-based block matching

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

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