Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136)
DOI: 10.1109/acssc.1997.680263
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Visualising reconfigurable libraries for FPGAs

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(2 citation statements)
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“…· Develop the most ecient implementation of the repeating units before hardware compilation, using device-speci®c descriptions like OAL if necessary. The system has been used in developing a number of regular array designs, including a systolic convolver [11], a systolic priority queue [9], a systolic sorter [10], a sine calculator [8], and in developing recon®gurable libraries for FPGAs [24,25]. It has also been used in producing implementations partly in hardware and partly in software [23].…”
Section: Resultsmentioning
confidence: 99%
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“…· Develop the most ecient implementation of the repeating units before hardware compilation, using device-speci®c descriptions like OAL if necessary. The system has been used in developing a number of regular array designs, including a systolic convolver [11], a systolic priority queue [9], a systolic sorter [10], a sine calculator [8], and in developing recon®gurable libraries for FPGAs [24,25]. It has also been used in producing implementations partly in hardware and partly in software [23].…”
Section: Resultsmentioning
confidence: 99%
“…Our visualiser has been used in developing hardware libraries and designs involving run-time recon®guration [25].…”
Section: The Visualisation Systemmentioning
confidence: 99%