Virtual Point-to-Point Connections for NoCs

Modarressi, Mehdi; Tavakkol, Arash; Sarbazi-Azad, Hamid

doi:10.1109/tcad.2010.2048402

Cited by 58 publications

(55 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…3) The effectiveness of the proposed hybrid scheme is demonstrated by comparing with the baseline packed switched NoC and VIP design [6] using a set of synthetic and real traffic workloads.…”

Section: ____________________________________________________________mentioning

confidence: 99%

“…Then, the long setup time will decrease the overall NoC performance. To address the problems of packet switching and circuit switching, the hybrid scheme [4]- [6] that combines packet switching and circuit switching is proposed. It not only can provide high flexibility for communications but also optimize latency of NoCs by establishing CS connections between communication pairs.…”

Section: Introductionmentioning

confidence: 99%

“…It not only can provide high flexibility for communications but also optimize latency of NoCs by establishing CS connections between communication pairs. It had been also demonstrated that establishing CS connections on the PS network can reduce communication power [6]. Moreover, before circuits have been established, packets are transmitted on PS connections to offset the long setup delay of circuits.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Minimization of Latency and Power for Network-on-Chip

Abhijeet¹

2015

IJRITCC

View full text Add to dashboard Cite

Abstract-Network-on-chip (NoC) has emerged as a imperative aspect that determines the performance and power consumption of many-core systems. This paper proposes a combination scheme for NoCs, which aims at gaining low latency and low power consumption. In the presented combination scheme, a peculiar switching mechanism, called virtual circuit switching, is proposed to interweave with circuit switching and packet switching. Flits traveling in virtual circuit switching can pass through the router with only one stage. In addition, multiple virtual circuit-switched (VCS) connections are granted to share a common physical channel. Moreover, a path allocation algorithm is used in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized.

show abstract

Section: ____________________________________________________________mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Minimization of Latency and Power for Network-on-Chip

Abhijeet¹

2015

IJRITCC

View full text Add to dashboard Cite

show abstract

“…Such scheme, however, incurs high communication latency and power consumption due to the contention for the shared channels, buffering, and long pipeline stages [8] [9]. Some of the existing approaches like the express virtual channel (EVC) [8] and the duo [10] try to bypass part of or full router pipeline stages so as to optimize data transmission.…”

Section: Introductionmentioning

confidence: 99%

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation

Wang

Mak

Yang

et al. 2013

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

View full text Add to dashboard Cite

Abstract-Modern networks-on-chip (NoC) systems are required to handle complex run-time traffic patterns and unprecedented applications. Data traffics of these applications are difficult to be fully comprehended at design-time so as to optimize the network design. However, it has been discovered that the majority data flows in a network are dominated by less than 10% of the specific pathways. In this paper, we introduce a method that is capable of identifying critical pathways in a network at run-time and, then, can dynamically reconfigure the network to optimize for the network performance subjected to the identified dominated flows. An online learning and analysis scheme is employed to quickly discover the emerged dominated traffic flows and provides a statistical traffic prediction using regression analysis. The architecture of a self-tuning network is also discussed which can be reconfigured by setting up the identified point-to-point paths for the dominance data flows in large traffic volumes. The merits of this new approach are experimentally demonstrated using comprehensive NoC simulators. Compared to the conventional network architectures over a range of realistic applications, the proposed self-tuning network approach can effectively reduce the latency and power consumption by as much as 25% and 24%, respectively. We also evaluated the configuration time and additional hardware cost. This new approach demonstrates the capability of an adaptive NoC to handle more complex and dynamic applications.

show abstract

“…VIP [Modarressi et al, 2010] is a hybrid network benefiting from the scalability and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. To build the hybrid interconnect, the following steps are done based on the application task graph: 1) physically map the tasks to different nodes of a 2D-mesh NoC; 2) construct the point-topoint links between the tasks as much as possible; 3) re-direct the flow for which messages are traveled following the point-to-point link in such a way that the power consumption and latency of the 2D-mesh NoC is minimized.…”

mentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

show abstract

Virtual Point-to-Point Connections for NoCs

Cited by 58 publications

References 27 publications

Minimization of Latency and Power for Network-on-Chip

Minimization of Latency and Power for Network-on-Chip

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Contact Info

Product

Resources

About