Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance

Yoon, Young Jin; Concer, Nicola; Petracca, Michele; Carloni, Luca P.

doi:10.1109/tcad.2013.2276399

Cited by 48 publications

(16 citation statements)

References 37 publications

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“…The design complexity of the SCCI depends on the scale of the ESP instance and may vary from a simple bus to a packet-switched network-on-chip (NoC), which can be further scaled up by adding more virtual channels and/or multiple physical planes [31]. In any case, the low-level details of its circuit mechanisms are transparent to both the SoC architects and component designers, who work at a higher level of abstraction relying on transaction-level modeling [15].…”

Section: A Scalable Architecturementioning

confidence: 99%

Invited - The case for embedded scalable platforms

Carloni

2016

Proceedings of the 53rd Annual Design Automation Conference

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Heterogeneous system-on-chip (SoC) architectures are emerging as a fundamental computing platform across a variety of domains, from mobile to cloud computing. Heterogeneity, however, increases design complexity in terms of hardware-software interactions, access to shared resources, and diminished regularity of the design. Embedded Scalable Platforms are a novel approach to SoC design and programming that addresses these design-complexity challenges by combining an architecture and a methodology. The flexible socketed architecture simplifies the integration of heterogeneous components by balancing regularity and specialization. The companion methodology raises the level of abstraction to system-level design, thus promoting closer collaboration among software programmers and hardware engineers. The architecture is supported by a scalable communication infrastructure. The methodology leverages compositional design-space exploration with high-level synthesis. The case for Embedded Scalable Platforms is made based on experiments on the development of various full-system prototypes and experience in teaching these concepts in a new graduate course.

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Section: A Scalable Architecturementioning

confidence: 99%

Invited - The case for embedded scalable platforms

Carloni

2016

Proceedings of the 53rd Annual Design Automation Conference

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“…Besides that large multiplexing width increases the area overhead and power consumption of a VC router in comparison to other alternatives such as Multiple Physical (MP) Networks. By partitioning physical channels across multiple independent networks, the MP NoC is able to remove the need for having such very wide multiplexers [27]. In our proposed design, to remove these large-width multiplexers, as suggested in [5], we implemented all IVCs buffers of an input port inside a single dual port memory, where one port of this memory is dedicated for writing the incoming flits and the other port is used for reading the desired flit which is going to be passed to the crossbar.…”

Section: Merging All Ivcs Buffers Of the Same Input Port In Onementioning

confidence: 99%

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

Monemi

Ooi

Marsono

2015

International Journal of Reconfigurable Computing

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Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

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“…• Computation: a secure application is mapped in dedicated Processing Elements (PEs), i.e., its tasks are not allowed to share a CPU with tasks belonging to other applications. • Communication: SDN-based management defines exclusive communicating paths for secure flows using a Multiple-Physical NoC (MPN) [17,18].…”

Section: Introductionmentioning

confidence: 99%

SDN-Based Secure Application Admission and Execution for Many-Cores

2020

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General-purpose many-core system-on-chip (MCSoC) requires support to the execution of dynamic workloads, i.e., admission of new applications at runtime. Some applications may require QoS and security from the MCSoC, not tolerating that malicious tasks or hardware Trojans steal or corrupts their data. A robust method to provide security is to isolate the communication and computation. Most current works employ such isolation in continuous regions named secure zones (SZ). Motivated by the recent study of the Software-Defined Networking (SDN) paradigm for MCSoCs, this work proposes to use SDN-based management to implement the communication isolation at runtime. The computation isolation occurs by mapping only tasks of the same application at each core. The communication isolation is supported by the SDN paradigm, which establishes dedicating paths for secure applications. Results show that the SDN-based approach presents a negligible latency to admit and execute a secure application, with a reduced hardware cost and higher computational resources utilization compared to SZs.

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Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance

Cited by 48 publications

References 37 publications

Invited - The case for embedded scalable platforms

Invited - The case for embedded scalable platforms

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

SDN-Based Secure Application Admission and Execution for Many-Cores

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