Video compression with parallel processing

Ahmad, Ishfaq; He, Ying; Liou, M.L.

doi:10.1016/s0167-8191(02)00100-x

Cited by 43 publications

(12 citation statements)

References 80 publications

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“…However, there are many general parallelization techniques for accelerating H.264 encoding, such as frame/slice level parallelism, wavelet/MB pipeline and fine granularity block parallelism [12]. Compared to streaming, these techniques only focus on data dependency of some level with the risk of side-effect.…”

Section: Discussionmentioning

confidence: 99%

Streaming HD H.264 encoder on programmable processors

Wen

et al. 2009

Proceedings of the 17th ACM International Conference on Multimedia

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Programmable processors have great advantage over dedicated ASIC design under intense time-to-market pressure. However, realtime encoding of high-definition (HD) H.264 video (up to 1080p) is a challenge to most existing programmable processors. On the other hand, model-based design is widely accepted in developing complex media program. Stream model, an emerging model-based programming method, shows surprising efficiency on many compute-intensive domains especially for media processing. On the basis, this paper proposes a set of streaming techniques for H.264 encoding, and then develops all of the code based on the X264 reference code. Our streaming H.264 encoder is a pure software implementation completely written in high-level language without special hardware/algorithm support. Real execution results show that our encoder achieves significant speedup over the original X264 encoder on various programmable architectures: on X86 Core TM 2 E8200 the speedup is 1.8x, on MIPS 4KEc the speedup is 3.7x, on TMS320 C6416 DSP the speedup is 5.5x, on stream processor STORM-SP16 G220 the speedup is 6.1x. Especially, on STORM processor, the streaming encoder achieves the performance of 30.6 frames per second for a 1080P HD sequence, satisfying the real-time requirement. These indicate that streaming is extremely efficient for this kind of media workload. Our work is also applicable for other media processing applications, and provides architecture insights into dedicated ASIC or FPGA HD H.264 encoders.

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Section: Discussionmentioning

confidence: 99%

Streaming HD H.264 encoder on programmable processors

Wen

et al. 2009

Proceedings of the 17th ACM International Conference on Multimedia

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“…Parallelization of the video compression algorithm has been studied both in hardware codec and software codec [22]. Hardware based parallel codec is usually implemented using dedicated VLSI and supports parallelization of a specific module in the encoding or decoding process [9]- [12].…”

Section: Related Workmentioning

confidence: 99%

Exploiting Thread-Level Parallelism on HEVC by Employing a Reference Dependency Graph

Kim

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

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This paper presents an optimized parallel algorithm for the next-generation video codec HEVC. The proposed method provides maximized parallel scalability by exploiting two levels of parallelism: frame-level and tasklevel. Frame-level parallelism is exploited by using a graph that efficiently provides a parallel coding order of the frames with complex reference dependencies. The proposed Reference Dependency Graph is generated at runtime by a novel construction algorithm that dynamically analyzes the configuration of the HEVC codec.Task-level parallelism is exploited to provide further scalability to frame-level parallelization. A pipelined execution is allowed for independent tasks, which are defined by dividing and categorizing a single coding process into multiple types of tasks. The proposed parallel encoder and decoder do not suffer from loss in coding efficiency because neither constraints nor modification in coding options are required. The proposed parallel methods result in an average encoding speedup of 1.75 and the aggressive method that exploits additional frame-level parallelism achieved 6.52 speedup using eight physical cores.Abstract-This paper presents an optimized parallel algorithm for the next-generation video codec HEVC. The proposed method provides maximized parallel scalability by exploiting two levels of parallelism: frame-level and task-level. Frame-level parallelism is exploited by using a graph that efficiently provides a parallel coding order of the frames with complex reference dependencies. The proposed Reference Dependency Graph is generated at runtime by a novel construction algorithm that dynamically analyzes the configuration of the HEVC codec. Tasklevel parallelism is exploited to provide further scalability to frame-level parallelization. A pipelined execution is allowed for independent tasks, which are defined by dividing and categorizing a single coding process into multiple types of tasks. The proposed parallel encoder and decoder do not suffer from loss in coding efficiency because neither constraints nor modification in coding options are required. The proposed parallel methods result in an average encoding speedup of 1.75 and the aggressive method that exploits additional frame-level parallelism achieved 6.52 speedup using eight physical cores.

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“…4. In order to minimize the effect of synchronization overhead due to data partitioning, it is preferable that each data partition processes larger data blocks [1]. 5.…”

Section: Optimization Guidelinesmentioning

confidence: 99%

UML for Modelling and Performance Estimation of Embedded Systems.

Boutekkouk¹,

Benmohammed²,

Bilavarn³

et al. 2009

JOT

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In this paper, we would like to present a new UML-based methodology for embedded applications design. Our approach starts from a pure sequential object paradigm model from which a task level model is extracted. The latter allows designer to expose all parallelism forms such as task parallelism, data parallelism, pipelining, while making control and communication over tasks explicit. Another particularity of our approach is hardware parameterization-based abstraction in which hardware platform is modelled as a set of generic components. Each component is parameterized by a set of abstract parameters matching the abstraction level of application. An estimation technique of performance is proposed. Since we are dealing with higher level of abstraction, the values of these metrics are not absolute, rather than, they are relative in the sense, we will use them to compare between possible alternatives.

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Video compression with parallel processing

Cited by 43 publications

References 80 publications

Streaming HD H.264 encoder on programmable processors

Streaming HD H.264 encoder on programmable processors

Exploiting Thread-Level Parallelism on HEVC by Employing a Reference Dependency Graph

UML for Modelling and Performance Estimation of Embedded Systems.

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