Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation

Platzer, Michael; Puschner, Peter

doi:10.4230/lipics.ecrts.2021.1

Cited by 14 publications

(4 citation statements)

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“…Vector processors promise improved energy efficiency for data-parallel workloads ( Platzer & Puschner, 2021 ). They also have the potential to reduce the performance gap between platforms suitable for time-critical applications and mainstream processors.…”

Section: Related Workmentioning

confidence: 99%

“…Thus, the IF/ID pipeline register will store the instruction fetched from program memory, the current PC value required for restart in case of an exception occurring in the next pipeline stages, and the PC+4 value required for fetching the next instruction. The IF_Stall, ID_Stall, IF_Exception_Flush, and IF_Flush signals are required by the control unit and the CPZero module ( Platzer & Puschner, 2021 ), allowing stalling and flushing of the pipeline in case of hazard situations and exceptions. Operands read from the GPR will be stored in the next pipeline stage if the instruction is of type R or I, or will be ignored as is the case for jump instructions.…”

Section: Custom Soft-core Processor Fpga Development and Integrationmentioning

confidence: 99%

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Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Zagan

Găitan

2023

PeerJ Computer Science

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One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.

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Section: Related Workmentioning

confidence: 99%

Section: Custom Soft-core Processor Fpga Development and Integrationmentioning

confidence: 99%

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Zagan

Găitan

2023

PeerJ Computer Science

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“…In [11,12], Hahn et al introduce SIC: a timing anomaly-free in-order core, as well as a formal modeling and proof framework. Using the same framework, [17] introduced Vicuna, a vector coprocessor that was proven free of timing anomalies. Finally [6,8] presented MINOTAuR, an open source RISC-V predictable core featuring a restricted degree of out-of-order execution as well as branch prediction mechanisms.…”

Section: Related Workmentioning

confidence: 99%

Enabling timing predictability in the presence of store buffers

Gruin

Carle

Rochange

et al. 2023

The 31st International Conference on Real-Time Networks and Systems

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“…Small-scale vector units have been proposed for Field-Programmable Gate Arrays (FPGAs), where the leanness of the vector processor is a constraint due to limited FPGA resources. Vicuna [15] is a timing-predictable vector processor compliant with RVV version 0.10, synthesized on a Xilinx Series 7 FPGA. Its VRF was implemented as a multi-ported Random-Access Memory (RAM) due to concerns with timing anomalies with a multi-banked VRF.…”

Section: Related Workmentioning

confidence: 99%

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters

Cavalcante¹,

Wüthrich²,

Perotti³

et al. 2022

Preprint

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While parallel architectures based on clusters of Processing Elements (PEs) sharing L1 memory are widespread, there is no consensus on how lean their PE should be. Architecting PEs as vector processors holds the promise to greatly reduce their instruction fetch bandwidth, mitigating the Von Neumann Bottleneck (VNB). However, due to their historical association with supercomputers, classical vector machines include microarchitectural tricks to improve the Instruction Level Parallelism (ILP), which increases their instruction fetch and decode energy overhead. In this paper, we explore for the first time vector processing as an option to build small and efficient PEs for large-scale shared-L1 clusters. We propose Spatz, a compact, modular 32-bit vector processing unit based on the integer embedded subset of the RISC-V Vector Extension version 1.0. A Spatz-based cluster with four Multiply-Accumulate Units (MACUs) needs only 7.9 pJ per 32-bit integer multiply-accumulate operation, 40% less energy than an equivalent cluster built with four Snitch scalar cores. We analyzed Spatz' performance by integrating it within MemPool, a large-scale many-core shared-L1 cluster. The Spatz-based MemPool system achieves up to 285 GOPS when running a 256 × 256 32-bit integer matrix multiplication, 70% more than the equivalent Snitch-based MemPool system. In terms of energy efficiency, the Spatz-based MemPool system achieves up to 266 GOPS/W when running the same kernel, more than twice the energy efficiency of the Snitch-based MemPool system, which reaches 128 GOPS/W. Those results show the viability of lean vector processors as high-performance and energy-efficient PEs for large-scale clusters with tightly-coupled L1 memory.

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Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation

Cited by 14 publications

References 0 publications

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Enabling timing predictability in the presence of store buffers

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters

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