Viable opto-electronic HPC interconnect fabrics

Luijten, Ronald P.; Minkenberg, Cyriel; Hemenway, Roe; Sauer, Matthias; Grzybowski, Richard

doi:10.1109/sc.2005.78

Cited by 33 publications

(17 citation statements)

References 20 publications

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“…The Optical Electrical Optical (OEO) conversions further add to the cost and power consumption of switches. Fully optical switches that do not require an OEO conversion can eliminate the costly transceivers, but per-port costs will likely be higher than an OEO switch due to the need to use exotic optical materials in the implementation [19].…”

Section: Circuit Switch Technologymentioning

confidence: 99%

Communication Requirements and Interconnect Optimization for High-End Scientific Applications

Kamil

Oliker

Pınar

et al. 2010

IEEE Trans. Parallel Distrib. Syst.

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The path toward realizing next-generation petascale and exascale computing is increasingly dependent on building supercomputers with unprecedented numbers of processors. To prevent the interconnect from dominating the overall cost of these ultrascale systems, there is a critical need for scalable interconnects that capture the communication requirements of ultrascale applications. It is, therefore, essential to understand high-end application communication characteristics across a broad spectrum of computational methods, and utilize that insight to tailor interconnect designs to the specific requirements of the underlying codes. This work makes several unique contributions toward attaining that goal. First, we conduct one of the broadest studies to date of high-end application communication requirements, whose computational methods include: finite difference, lattice Boltzmann, particle-in-cell, sparse linear algebra, particle-mesh ewald, and FFT-based solvers. Using derived communication characteristics, we next present the fit-tree approach for designing network infrastructure that is tailored to application requirements. The fit-tree minimizes the component count of an interconnect without impacting application performance compared to a fully connected network. Finally, we propose a methodology for reconfigurable networks to implement fit-tree solutions. Our Hybrid Flexibly Assignable Switch Topology (HFAST) infrastructure, uses both passive (circuit) and active (packet) commodity switch components to dynamically reconfigure interconnects to suit the topological requirements of scientific applications. Overall, our exploration points to several promising directions for practically addressing the interconnect requirements of future ultrascale systems.

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Section: Circuit Switch Technologymentioning

confidence: 99%

Communication Requirements and Interconnect Optimization for High-End Scientific Applications

Kamil

Oliker

Pınar

et al. 2010

IEEE Trans. Parallel Distrib. Syst.

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“…An optical switching gate, for example, is switched only at the packet rate, and the power expended to control it is independent of the amount of data routed through it. Optical interconnection networks of various structures and topologies have therefore been suggested as solutions for HPC interconnection networks [13]- [17].…”

Section: Introductionmentioning

confidence: 99%

An Experimental Validation of a Wavelength-Striped, Packet Switched, Optical Interconnection Network

Shacham¹,

Bergman

2009

J. Lightwave Technol.

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Abstract-We experimentally validate a complete optical packet switched interconnection network, implementing the SPINet architecture. The scalable photonic integrated network (SPINet) architecture capitalizes on wavelength division multiplexing (WDM) to provide very large transmission bandwidths, simplify network design, and reduce the network's power dissipation. Contention resolution is performed in the optical domain, and a novel physical layer acknowledgement protocol is employed to mitigate the associated latency and performance penalties. Moreover, the SPINet architecture is specifically designed to enable on-chip integration by not using any kind of optical delay lines. Experiments presented include a complete functionality verification, error-free routing of 80 Gb/s wavelength-striped optical packets (8 wavelengths each modulated at 10 Gb/s) with a bit-error rate (BER) better than 10 12 , and novel performance-enhancement techniques such as path adjustments and load balancing.Index Terms-Multistage interconnection networks, multiprocessor interconnection, optical interconnections, photonic switching systems.

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“…In the OSMOSIS project [16], the control overhead of the request and grant process was reduced by adding a speculative allocator operated in parallel with the scheduled allocator. Thus if any network adapter does not have a grant in a given time slot, it sends out a request and packet anyway which is dropped if there is no path available on the switch in that slot period (Fig.…”

Section: Scheduled and Speculative Networkmentioning

confidence: 99%

Energy Implications of Photonic Networks With Speculative Transmission

Watts¹,

Moore²,

Moore³

2012

J. Opt. Commun. Netw.

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Abstract-Speculative transmission has been proposed to overcome the high latency of setting up end-to-end paths through photonic networks for computer systems. However, speculative transmission has implications for the energy efficiency of the network, in particular, control circuits are more complex and power hungry and failed speculative transmissions must be repeated. Moreover, in future chip multiprocessors (CMPs) with integrated photonic network end points, a large proportion of the additional energy will be dissipated on the CMP. This paper compares the energy characteristics of scheduled and speculative chip-to-chip networks for shared memory computer systems on the scale of a rack. For this comparison, we use a novel speculative control plane which reduces energy consumption by eliminating duplicate packets from the allocation process. In addition, we consider photonic power gating to reduce processor chip energy dissipation and the energy impact of the choice between semiconductor optical amplifier and ring resonator switching technologies. We model photonic network elements using values from the published literature as well as determine the power consumption of the allocator and network adapter circuits, implemented in a commercial low leakage 45 nm CMOS process. The power dissipated on the CMP using speculative networks is shown to be roughly double that of scheduled networks at saturation load and an order of magnitude higher at low loads.

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Viable opto-electronic HPC interconnect fabrics

Cited by 33 publications

References 20 publications

Communication Requirements and Interconnect Optimization for High-End Scientific Applications

Communication Requirements and Interconnect Optimization for High-End Scientific Applications

An Experimental Validation of a Wavelength-Striped, Packet Switched, Optical Interconnection Network

Energy Implications of Photonic Networks With Speculative Transmission

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