Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon

Henry, David D.; Baillin, Xavier; Lapras, V.; Vaudaine, M.-H.; Quemper, Jean-Marie; Sillon, N.; Dunne, B.; Hernandez, C.; Vigier-Blanc, E.

doi:10.1109/ectc.2007.373894

Cited by 29 publications

(12 citation statements)

References 7 publications

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“…The advanced packaging solutions based on thin silicon carrier and Through Silicon Via (TSV), which provides vertical interconnects in stacked ICs, are being developed to interconnect integrated circuits and other devices at high densities [4][5].…”

Section: Introductionmentioning

confidence: 99%

Polysilicon interconnections (FEOL): Fabrication and characterization

Agarwal

Murthy

Lee

et al. 2009

2009 11th Electronics Packaging Technology Conference

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Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is Through Silicon Via (TSV), which can provide vertical interconnects in stacked ICs. In this paper, we present vias-first process to realize vertical interconnects that is fully FEOL compatible. The vias are filled by doped polysilicon and wafers with such pre-fabricated vias can be used as the starting wafers for any CMOS device processing. The process details and their characterization are elaborated along with the physical and electrical analysis of such vias. IntroductionAs the conventional CMOS scaling is becoming more challenging and less beneficial [1-3], the three dimensional silicon integration technologies are gaining significant importance. The advanced packaging solutions based on thin silicon carrier and Through Silicon Via (TSV), which provides vertical interconnects in stacked ICs, are being developed to interconnect integrated circuits and other devices at high densities [4][5].TSV Technologies are generally grouped as vias-first process and vias-last process. As the name suggests, in the vias-first process the deep via is etched by reactive-ion etching, insulation is provided by SiO 2 deposition or high temperature thermal oxidation, and vias are filled by doped polysilicon. Conductors like plated Copper, Copper with ceramic composites or tungsten deposited by chemical vapor deposition are also used to fill vias but they are not compatible to many of front-end-of line (FEOL) processes. Vias-first are realized at the earlier stages of fabrication and are compatible to FEOL processes which is a great advantage for integrated device and interconnect realization. The TSVs are exposed using mechanical grinding and polishing from the back-side of the wafers, followed by insulation, via exposure and final joining metallurgy steps complete the process. On-other-hand, the vias-last process starts with standard FEOL and BEOL processes have previously been used to build devices and wiring levels. A handler is attached to the wafer front and it is thinned from the back. Using backside lithography, the TSVs are defined and etched, landing on an etch stop layer that is typically a dielectric perforated with metal or silicide contact pads. The vias are insulated using low-temperature BEOL compatible processes, after which the contact pads at the base of the vias are exposed to allow metallization. Copper plating is typically used to fill the vias. Vias-last process is facing multiple challenges such as it needs backside lithography, a low-temperature conformal insulation process and a method to etch the insulation at the base of the vias to realize reliable electrical connections. Moreover, these are packaging solutions for a fully fabric...

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Section: Introductionmentioning

confidence: 99%

Polysilicon interconnections (FEOL): Fabrication and characterization

Agarwal

Murthy

Lee

et al. 2009

2009 11th Electronics Packaging Technology Conference

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“…For example, in [12] and [29], via-first TSV technology has been investigated with little attention on circuit design implications. Similarly, via-middle TSVs have been discussed in [14][15][16] focusing primarily on process characteristics.…”

Section: Previous Workmentioning

confidence: 99%

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Satheesh

Salman

2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Electrical Engineering Stony Brook University 2012Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance.iii To my dearest parents, Jayashree Krishnamurthy and Satheesh Lakshminarayana.

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“…Then, a new process has been developed and improved after the first morphological characterizations, especially for deep etching and void-free polysilicon filling [13]. Morphological characterization and electrical tests have been already presented in a previous paper [14]. A thermal simulation of flip-chip reflows generally used for back-end technology has ben achieved on these vias.…”

Section: Introductionmentioning

confidence: 98%

High Aspect Ratio Vias First for Advanced Packaging

Henry

Baillin

Lapras

et al. 2007

2007 9th Electronics Packaging Technology Conference

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In this paper a new 'via-first' technology which is compatible with CMOS high temperature steps will be presented. This technology is based on filling high aspect ratio trenches with doped polysilicon and thinning the silicon after active device bonding onto a wafer carrier. The initial morphological requirements are described and different designs of TSV are presented. The complete technology for TSV achievement is described in detail and electrical results obtained with different vias geometries are presented and compared to initial calculations. Finally, several reflows experiments have been performed on these vias and electrical measurements have been achieved again and compared to initial results.

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Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon

Cited by 29 publications

References 7 publications

Polysilicon interconnections (FEOL): Fabrication and characterization

Polysilicon interconnections (FEOL): Fabrication and characterization

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

High Aspect Ratio Vias First for Advanced Packaging

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