VHDL transition from system to detailed design

Arsenault, K.; Wong, Joyce; Cohen, Mitchell A.

doi:10.1109/tcc.1990.177820

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…Several translation schemes have been published for translating a variety of speci cation languages to VHDL 8,9,10,11,12,13,14]. These languages support a very di erent model than SpecCharts or support only a subset of the embedded-system characteristics outlined in Section 2.…”

Section: Vhdl Translation Algorithmmentioning

confidence: 99%

SpecCharts: a VHDL front-end for embedded systems

Vahid

Narayan²,

Gajski³

1995

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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VHDL and other hardware description languages are commonly used as speci cation languages during system design. However, the underlying model of those languages does not directly support the speci cation of embedded systems, making the task of specifying such systems tedious and errorprone. We introduce a new conceptual model, called Program-State Machines (PSM), that caters to embedded systems. We describe SpecCharts, a VHDL extension that supports capture of the PSM model. The extensions we describe can also be applied to other languages. SpecCharts can be easily incorporated into a VHDL design environment using automatic translation to VHDL. We highlight several experiments that demonstrate the advantages of signi cantly reduced speci cation time, fewer errors, and improved speci cation readability.

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Section: Vhdl Translation Algorithmmentioning

confidence: 99%

SpecCharts: a VHDL front-end for embedded systems

Vahid

Narayan²,

Gajski³

1995

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Thus many translation schemes have appeared from domain specific languages to VHD L [ArWC90,DuCH91,MaWa90,NaVG91,JePA91,TiLK90]. Intended uses for the generated VHDL include documentation, simulation, and/or synthesis.…”

Section: Introductionmentioning

confidence: 99%

Obtaining functionally equivalent simulations using VHDL and a time-shift transformation

Vahid

Gajski

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

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The advent of VHDL has brought about a number of VHDL simulators. Many translation schemes from domain specific languages to supposedly equivalent VHDL have been developed as an approach to obtaining simulations. However, functionally equivalent VHDL can not be created for the general case, due to a theoretical limitation to this approach. It is a very subtle point and has thus been overlooked until now, but it is extremely important since it can cause incorrect simulation, therefore making translations to VHDL an unsound simulation technique. In this paper, we introduce this fundamental limitation. In addition, we propose an alternative approach which strives for functionally equivalent simulation rather than functionally equivalent VHDL, while still taking advantage of VHDL simulators. Our method uses a novel time-shift transformation, also introduced in this paper, in conjunction with almost any translation scheme. The method makes correct simulations easily obtainable, thus bridging the gap to a truly sound nnd highly advantageous use of VHDL as r1 tool for simulating domain specific languages.

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