VHDL implementation of IEEE 754 floating point unit

Anjanasasidharan,; Nagarajan, Prabhat

doi:10.1109/icices.2014.7033999

Cited by 7 publications

(7 citation statements)

References 3 publications

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“…In addition, our proposal is evaluated in FPGA. Still, it is important to mention that there are Commercial Reconfigurable Processors [ 43 ] or Systems on Chip integrating FPGA [ 44 , 45 , 46 , 47 ] and FPGAs that have been integrating Processing Cores for years. Therefore, it is possible to integrate our solution in vehicular systems as well as in industrial, business, or home systems, as we show in Figure 3 .…”

Section: Methodsmentioning

confidence: 99%

Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models

Torres-Alvarado

Morales-Rosales

Algredo‐Badillo

et al. 2022

Sensors

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The latest generation of communication networks, such as SDVN (Software-defined vehicular network) and VANETs (Vehicular ad-hoc networks), should evaluate their communication channels to adapt their behavior. The quality of the communication in data networks depends on the behavior of the transmission channel selected to send the information. Transmission channels can be affected by diverse problems ranging from physical phenomena (e.g., weather, cosmic rays) to interference or faults inherent to data spectra. In particular, if the channel has a good transmission quality, we might maximize the bandwidth use. Otherwise, although fault-tolerant schemes degrade the transmission speed by solving errors or failures should be included, these schemes spend more energy and are slower due to requesting lost packets (recovery). In this sense, one of the open problems in communications is how to design and implement an efficient and low-power-consumption mechanism capable of sensing the quality of the channel and automatically making the adjustments to select the channel over which transmit. In this work, we present a trade-off analysis based on hardware implementation to identify if a channel has a low or high quality, implementing four machine learning algorithms: Decision Trees, Multi-Layer Perceptron, Logistic Regression, and Support Vector Machines. We obtained the best trade-off with an accuracy of 95.01% and efficiency of 9.83 Mbps/LUT (LookUp Table) with a hardware implementation of a Decision Tree algorithm with a depth of five.

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Section: Methodsmentioning

confidence: 99%

Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models

Torres-Alvarado

Morales-Rosales

Algredo‐Badillo

et al. 2022

Sensors

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“…The basic idea about an IEEE 754-2008 FPU is obtained from [1]. It discusses the bitwise representation of single and double precision format of the aforementioned standard.…”

Section: Ieee 754-2008 Floating Point Unitmentioning

confidence: 99%

“…The multiplier block shown in figure 1, is used in various multipliers. But multiplier schemes such as Booth, Vedic, shift-add [1] do not work for a certain class of numbers. These numbers are exceptions.…”

Section: Exceptionsmentioning

confidence: 99%

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Design of a Novel Fused Add-Sub Module for IEEE 754-2008 Floating Point Unit in High Speed Applications

Bisoyi¹,

Tripathy²

2020

CAE

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A multiplier block can be implemented either by shift add technique, Booth algorithm or Vedic algorithm, in DSP applications. However, these techniques do not work for a certain class of numbers known as exceptions. They are +infinity,-infinity and Not a Number (NaN). The solution to address these exceptions is a "Fused add-subtract" module. The addition and subtraction modules are fused together to give two outputs giving both addition and subtraction results. The time delay and the number of Look-Up Tables (LUTs) of the existing Fused add-subtract unit have been found to be quite high to meet the present-day requirements of speed. Therefore, a novel algorithm for fused add-subtract has been proposed in this paper. In the floating-point unit (FPU), building blocks of the addition and subtraction are fused together, resulting in reduction of the number of computations as well as the area usage. The existing fused add-sub module is compared with the proposed module in terms of delay and the number of LUTs. The new algorithm is observed to reduce the time delay and area by 12.5% and 18.878% respectively as compared to the conventional one.

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“…and Nagarajan, M.P. [14]. The floatingpoint data are usually use on different software and hardware.…”

Section: Communication To Computermentioning

confidence: 99%

Remote Monitoring L.V. Switchboard Power Status with 5G New Radio Network Application

Tsang¹,

Chung²

2019

IJCSIT

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In a power distribution system of most of the buildings, A Low Voltage (L.V.) switchboard was applied to protect the system. There are different components in the switchboard (e.g. circuit breakers, over current protection relay, earth fault protection relay etc.). There are also some components for measure the power quality which is the power analyser. A power analyser (including Voltmeter, Ammeter, Multi-meter) is using to measure the power quality in the electrical power distribution system. Most of the electrical power distributions systems have been connected the power analysers to a building management system. The power analysers connected to a computer in a fixed position that means if someone wants to check the power distribution status, the person needs to go to the computer to check. In this project, a system would be made to monitoring the power status by 5G New Radio (NR) Network application with android smartphone. Since 5G NR Network can provide a theoretical peak download capacity of 20 Gigabits per second. It would be more convenient to monitoring the power status in different place by checking though in the Internet of Things (IoT) . KEYWORDSLow Voltage (L.V.) switchboard, 5G New Radio (NR) Network, Internet of Things, Mobile Network.

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VHDL implementation of IEEE 754 floating point unit

Cited by 7 publications

References 3 publications

Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models

Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models

Design of a Novel Fused Add-Sub Module for IEEE 754-2008 Floating Point Unit in High Speed Applications

Remote Monitoring L.V. Switchboard Power Status with 5G New Radio Network Application

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