VHDL Implementation of Capacitor Voltage Balancing Control with Level-Shifted PWM for Modular Multilevel Converter

Abstract

Power electronics converters are a key component in high voltage direct current (HVDC) power transmission. The modular multilevel converter (MMC) is one of the latest topologies to be proposed for this application. An MMC generates multilevel output voltage waveforms which reduces the harmonics contents significantly. This paper presents a VHDL implementation of the capacitor voltage balancing control and level-shifted pulse width modulation (LSPWM) for MMC. The objective is to minimize the processing time with minimum gate counts. The design details are fully described and validated experimentally. An experiment is conducted on a small scale MMC prototype with two units of power cells on each arm. The test results are enclosed and discussed.

Comparative study of two potential recuperating converters in DC railway electrification system for harmonic mitigation

“…Therefore, this paper choose to evaluate the converters using Level-Shifted-PWM modulation. This technique uses identical carrier wave for modulation, which is highly suitable for FPGA implementation [21]. The operation principle and Level-Shifted-PWM schemes of CHB and MMC will be summarized in the following sub-sections.…”

Harmonic Mitigation in Traction Supply Substation Using Cascaded H-Bridge Converter

“…Symmetric Cascaded H-Bridge converter has been investigated with different types of modulation techniques, such as Space Vector Modulation (SVM) [12], Selective Harmonic Elimination (SHE) [7], [13], Selective Harmonic Mitigation (SHM) [14], and Sinusoidal Pulse Width Modulation (SPWM) [15], [16]. Among all, SPWM technique is simpler to be implementated [17]. A sinusoidal wave (control signal) is compared with a series of high frequency triangular waves to generate specific gating signals.…”