VHDL generation from hierarchical Petri net specifications of parallel controllers

Control Interpreted Petri Nets - Model Checking and Synthesis

“…Proposed approach is an inertial description oriented on transitions (based on publications [1]. In the paper [11] Output signals from the net in Figure 6 are therefore assigned to places, in which they are active ( Figure 8). For example, the y10 output signal is active only by active marking of the p2 place, and active marking of the p10 place implies the activity of output signals y4, y5 and y6.…”

Digital systems synthesis from Petri net descriptions

“…Another work describes an electronic computer aided design framework (SCBA) for the specification, validation, and high level synthesis of synchronous interpreted Petri nets (SIPN) based controller [49] . SIPN is an extension of ordinary Petri nets, to accomplish the specification of asynchronous parallel controllers.…”

“…SIPN is an extension of ordinary Petri nets, to accomplish the specification of asynchronous parallel controllers. Within this framework, reachability graph analysis of the SIPN description is used to investigate the properties of the modeled system [49] . A compiler automatically translates the SIPN specification into a register transfer level VHDL description that is used for simulation and synthesis purposes by a package that accepts the VHDL subset generated by the compiler [41] .…”

Translating Synchronous Petri Nets into PROMELA for Verifying Behavioural Properties

“…In general, the major weakness of PNs is the complexity problem; PN-based models tend to become too large for analysis even for a small real system [8]. In [5] reachability graph analysis of the SIP-net description is used to investigate the properties of the modeled system.…”

“…Synchronous and Interpreted Petri Nets (SIP-nets) were obtained by the enrichment of safe PNs with guarded transitions, synchronous firing, and also enabling and inhibitor arcs [5]. With these characteristics, the models that can be obtained are easier to synthesize [6].…”