VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators

Abstract

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

On the synchronization techniques of chaotic oscillators and their FPGA-based implementation for secure image transmission

“…The electronic implementations of these chaotic oscillators were performed herein by exploiting the advantages of the field-programmable gate arrays (FPGAs) for fast prototyping [32]. As already detailed in [33], the mathematical equations modeling a chaotic oscillator can be described through the hardware description language (HDL), which in this work we use the tool Active-HDL. In this manner, the chaotic oscillators are implemented with adders, subtractors and multipliers, as detailed in [32].…”

“…In addition, a PWL function having the forms shown in Fig 1 can be implemented with comparators. The HDL code can be generated according to [33], where it is highlighted that the size of the digital blocks require the number of bits being used, and in this case we use fixed-point notation with format 7.21.…”

FPGA Realization of Spherical Chaotic System with Application in Image Transmission

“…is important characteristic not only makes FPGAs reusable but also makes them adaptable, extremely cost effective, and perfect choice for prototyping purposes. Furthermore, the design process of the FPGAs, performed by hardware description languages (HDLs), is extremely fast and efficient [38].…”

Complexity of Simple, Switched and Skipped Chaotic Maps in Finite Precision

“…The effect of numerical discretization over a chaotic map was recently addressed in [ 3 , 9 , 10 , 11 ]. In our previous work [ 3 ] we have explored the statistical degradation of the phases’ space for a family of 2D quadratic maps.…”

“…Nepomuceno et al [ 9 ] reported the existence of more than one pseudo-orbit of continuous chaotic systems when it is discretizated using different schemes. In [ 10 ] and [ 11 ], authors have proposed to use the value of the entropy to choose the number of bits in the fractional part, when maps are implemented in integer arithmetic.…”