VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers

Janiszewski, I.; Hoppe, Berthold; Meuth, H.

doi:10.1109/dac.2001.935574

Cited by 6 publications

(4 citation statements)

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“…While the CORDIC algorithm may result in arbitrary precision, although at the expense of pipeline latency and internal bit resolution overhead, the alternative of using standard Look-Up Table (LUT) solutions leads to a silicon area rapidly increasing with bit-resolution, although with only moderate or no latency, as was discussed in detail for the rotation mode in [4], [5], [6]. For the vectoring mode, requiring a two-dimensional input for x and y, the resulting more complex LUT approach quickly grows out of proportion.…”

Section: Hybrid-vectoring Schemementioning

confidence: 97%

“…Unfortunately, these functions are not directly synthesizable, even when used for only obtaining values for an integer range constant. A workaround solution for this, which also may be realized in a standard HDL simulation environment, is the possibility to generate a VHDL package, which includes all needed constants via an HDL simulation, by invoking the standard textio andor std-logic-textio package, and, very essentially, the math-real package from the IEEE library, [5]. This procedure was used as principle work flow for our designs.…”

Section: Xymentioning

confidence: 99%

“…In earlier work, [4], [5], [6], a new hybrid scheme for the rotation mode was developed, effectively combining both advantages of CORDIC and LUT sshemes, whereby the preceding LUT eliminates a certain number of CORDIC iterations. Optimum partitioning between LUT and CORDIC, depending on resolution and other configuration parameters, produced designs of favorable silicon area and power consumption, available in a fully portable and parametrically configurable HDL format.…”

Section: Hybrid-vectoring Schemementioning

confidence: 99%

“…If a particular application requires the actual magnitude value (l), the value resulting from the x-path has to be rescaled correspondingly by one single multiplication at the end. This specific COR-DIC problem can be circumvented only for the rotation mode by initializing the iteration sequence with suitably rescaled starting values for x and y, [3], [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

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Pipeline-efficient hybrid vectoring implementation

Janiszewski

Meuth

Hoppe

Proceedings of the 2002 IEEE International Frequency Control Symposium and PDA Exhibition (Cat. No.02CH37234)

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Silicon area, power consumption and pipeline-emciency are investigated for hardware implementations of a Cartesian-to-polar (Le. both magnitude and phase) coordinate transformer (C2P). A novel hybrid scheme, consisting of both look-up and algorithmic constituents, is proposed, based on the VECTORING mode of the Coordinate Rotation Dlgital Computer (CORDIC) hardware algorithm, preceded by a principal axes transformation algorithm-derived look-up scheme. The iterative CORDIC algorithm is rigorous for infinite bit resolution, permitting in principle arbitrary precision, while its intrinsic sequential nature entails a substantial pipeline latency, and a high resolution overhead to combat finite iteration quantization error accumulation. Look-Up Table (LUT) size, due to the two Cartesian input dimensionality, increases rapidly with resolution and is thus limited to a small-resolution input data regime. Signal latencies may become essential e.g. for C2P inside a feedback loop. With the present hybrid scheme, numbers of iterations may be reduced by up to 50%, at no penalty or even at a reduction of silicon area and power consumption. Finally, such a hybrid architecture permits technology independent HDL models, a prerequisite for full portability and reuse.

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Section: Hybrid-vectoring Schemementioning

confidence: 97%

Section: Xymentioning

confidence: 99%