VEST - An intelligent tool for timing SoCs verification using UML timing diagrams

Pułka, Andrzej; Milik, Adam

doi:10.1109/fdl.2008.4641432

Cited by 5 publications

(3 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Pulka et al [11] utilized the usefulness of timing diagrams to show simulation results for timing verification in system on chip. With the same purpose, Binh et al [12] extracted timing constraints from timing diagrams to verify the conformity between the implementation and its requirement specification.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Automatic construction of timing diagrams from UML/MARTE models for real-time embedded software

Jee

Choi²,

Bae

2014

Proceedings of the 29th Annual ACM Symposium on Applied Computing

View full text Add to dashboard Cite

Analysis of timing constraints is an essential part in developing real-time embedded software. Performing the timing analysis during the early development phases prevents timing violations and enhances software quality. In the development of real-time embedded software, UML timing diagrams can play a significant role since they can provide not only intuitive specifications for timing constraints, but also valuable information for verifying system requirements. However, as software complexity increases, modeling timing diagrams is becoming difficult and costly. We propose an automated construction approach of timing diagrams from UML sequence diagrams and state machine diagrams with MARTE annotations. The proposed approach enables developers of RTES to save time required for modeling timing diagrams and prevents making mistakes in construction of timing diagrams.

show abstract

Section: Related Workmentioning

confidence: 99%

“…Despite the advantages of UML timing diagram, the number of studies on this diagram is still limited [11][12] [13][14] [15].…”

Section: Related Workmentioning

confidence: 99%

Automatic construction of timing diagrams from UML/MARTE models for real-time embedded software

Jee

Choi²,

Bae

2014

Proceedings of the 29th Annual ACM Symposium on Applied Computing

View full text Add to dashboard Cite

show abstract

“…The UML is a widely used general-purpose modeling language in the field of software engineering and it is the chosen modeling language for our approach. Studies conducted in [10], [11], and [12] use general-purpose UML for modeling embedded software. Apart from the generalpurpose UML, the UML profiles [3] such as Modeling and Analysis of Real-time and Embedded Systems (MARTE) consist of new stereotypes specific for the real-time and embedded system domain.…”

Section: Related Workmentioning

confidence: 99%

An architecture for deploying model based testing in embedded systems

Iyenghar

Westerkamp

Wuebbelmann

et al. 2010

2010 Forum on Specification &Amp; Design Languages (FDL 2010)

View full text Add to dashboard Cite

There have been several model based approaches used in the recent past for alleviating complexity in design, development and test case generation for real-time embedded software systems. However, deploying/executing these test cases in the embedded target without affecting the real-time behavior of the system still remains a challenging and unanswered question. To address this, we propose a novel architecture to perform an integrated model based testing for embedded systems. We introduce a holistic model based design, development and testing approach with the aid of a monitor and target debugger solution for real-time embedded systems. Our proposed approach eliminates the need for dynamic source code instrumentation inserted into the target to execute the software test routines. This will result in preserving the real-time behavior which is a boon especially for real-time critical and code size constrained embedded systems. We illustrate our proposed approach with a prototype and an example.

show abstract

Multithread RISC architecture based on programmable interleaved pipelining

Pułka

Milik

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

View full text Add to dashboard Cite

VEST - An intelligent tool for timing SoCs verification using UML timing diagrams

Cited by 5 publications

References 8 publications

Automatic construction of timing diagrams from UML/MARTE models for real-time embedded software

Automatic construction of timing diagrams from UML/MARTE models for real-time embedded software

An architecture for deploying model based testing in embedded systems

Multithread RISC architecture based on programmable interleaved pipelining

Contact Info

Product

Resources

About