Very Low Voltage (VLV) Design

Bertran, Ramon; Bose, Pradip; Brooks, David; Burns, J.L.; Buyuktosunoglu, Alper; Chandramoorthy, Nandhini; Cheng, Eric; Cochet, Martin; Eldridge, Schuyler; Friedman, Daniel; Jacobson, Hans; Joshi, Rajiv V.; Mitra, Subhasish; Montoye, Robert K.; Paidimarri, Arun; Parida, Pritish R.; Skadron, Kevin; Stan, Mircea R.; Swaminathan, Karthik; Vega, Augusto; Venkataramani, Swagath; Vezyrtzis, Christos; Wei, Gu-Yeon; Wellman, John-David; Ziegler, Matthew M.

doi:10.1109/iccd.2017.105

Cited by 6 publications

(3 citation statements)

References 24 publications

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“…As can be seen, VC707 exhibits the worst fault rate, up to 652 fault per 1 Mbit, which can be the consequence of the adopted architectural and technological performance optimization techniques, by the vendor. Also, a significant 1 Since the overall fault rates are very small, instead of percentage (%), we present them in terms of number of faults per 1Mbit, for clearer charts. difference is observed between the two KC705 platforms, i.e., KC705-A and KC705-B.…”

Section: B Power and Reliability Trade-off Of Fpga Brams Through Undermentioning

confidence: 99%

“…However, in real-world applications, these voltage margins are unnecessarily conservative and eliminating them can directly deliver significant power and energy efficiency. In recent years, it has been shown that aggressive undervolting, i.e., supply voltage underscaling below the standard nominal level can substantially improve the energy efficiency of real hardware including CPUs [1], [2], [3], [4], [5], [6], GPUs [7], ASICs [8], DRAMs [9], and SRAMs [10]. This paper extends the aggressive undervolting approach for commercial FPGAs.…”

Section: Introductionmentioning

confidence: 99%

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Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories

Salami

Ünsal

Kestelman

2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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In this work, we evaluate aggressive undervolting, i.e., voltage scaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip vendors to ensure the worst-case process and environmental scenarios. Through experimenting on several FPGA architectures, we measure this voltage guardband to be on average 39% of the nominal level, which in turn, delivers more than an order of magnitude power savings. However, further undervolting below the voltage guardband may cause reliability issues as the result of the circuit delay increase, i.e., start to appear faults. We extensively characterize the behavior of these faults in terms of the rate, location, type, as well as sensitivity to environmental temperature, with a concentration of on-chip memories, or Block RAMs (BRAMs). Finally, we evaluate a typical FPGA-based Neural Network (NN) accelerator under low-voltage BRAM operations. In consequence, the substantial NN energy savings come with the cost of NN accuracy loss. To attain power savings without NN accuracy loss, we propose a novel technique that relies on the deterministic behavior of undervolting faults and can limit the accuracy loss to 0.1% without any timing-slack overhead.• This paper is the first effort to empirically study aggressive voltage underscaling of FPGAs below the standard nominal level. Through experimenting on four FPGA platforms, we confirm a large guardband, which is measured to be on average 39% of the nominal level for © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

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Section: B Power and Reliability Trade-off Of Fpga Brams Through Undermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories

Salami

Ünsal

Kestelman

2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…Therefore, characterization of these undervolting faults and understanding their behavior is critical to mitigate their impact. Although, there have been some previous undervolting works on CPUs [3], Graphic Processor Units (GPUs) [4], and Dynamic RAM (DRAM) memories [5], there are no "deep-dive" undervolting fault characterization studies due to the relatively closed nature of these hardware substrates where the vendors expose few details. In comparison, the relatively open Field Programmable Gate Array (FPGA) architectures make it possible to conduct and report such detailed studies.…”

Section: Introductionmentioning

confidence: 99%

Fault Characterization Through FPGA Undervolting

Salami

Ünsal

Cristal

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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The power and energy efficiency of Field Programmable Gate Arrays (FPGAs) are estimated to be up to 20X less than Application Specific Integrated Circuits (ASICs). What is needed to close this gap is aggressive power/energy savings techniques. A such potentially effective approach is undervolting, which can directly deliver an order of magnitude static and dynamic power savings. However, aggressive undervolting, without accompanying frequency scaling leads to timing related faults, potentially undermining the power savings. Understanding the behavior of these faults and efficiently mitigate them can deliver further power and energy savings in low-voltage designs without performance degradation. In this paper, we conduct a detailed analysis of undervolting FPGA BRAM structures. Through experimental analysis, we found that lowering the supply voltage until a certain conservative level, Vmin, does not introduce any observable fault. For the studied platforms, we measured this voltage guardband gap 39% of the nominal level (Vnom = 1V , Vmin = 0.61V). Further undervolting corrupts some of the data bits stored in BRAMs; however, it also reduces the BRAMs power consumption a further 40%. When the voltage is lowered below Vmin, the rate of these faults exponentially increases to 0.06%, by a fully non-uniform distribution over various BRAMs. This paper comprehensively analyzes the behavior of these faults.

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