Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation

Yin, Xiaogen; Yang, Hong; Xie, Lu; Ai, Xuezheng; Zhang, Y. B.; Jia, Kunpeng; Wu, Zhenhua; L., X.; Zhang, Q. Z.; Mao, Shujuan; Xiang, Jinjuan; Zhang, Yongkui; Gao, Jianfeng; He, Xiaobin; Bai, G. B.; Lu, Yihong; Zhou, Na; Kong, Zhenzhen; Zhang, Yongzheng; Zhao, Jianwen; S., S.; Xuan, Zihao; Zhu, Huilong; Li, Y. Y.; Li, L.; Zhang, Q. H.; Han, Jing; chen, rongqiang; Yu, Qian; Yang, Tao; Luo, Jun; Li, J. F.; Yin, Huaxiang; Wang, G. L.; Radamson, Henry H.; Zhao, Chao; Wang, W. W.; Ye, Tianchun; Li, J. J.; Du, Anyan; Li, Chen; Zhao, Li-Chen; Huang, Weixing

doi:10.1109/led.2019.2954537

Cited by 53 publications

(52 citation statements)

References 16 publications

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“…We emphasize that this is the first study that discusses an optimal interconnect structure The latest reports on the comparison between H-FETs and V-FETs show better driving current capability of H-FETs [37]. However, [37] also reports that there is a great potential for V-FETs that this performance gap will be reduced soon. [29], [38], and (b): Our structure and schematic.…”

Section: Interconnect Structure and Circuit Design For Many-tiermentioning

confidence: 83%

“…V-FETs are described by their name because their channels are constructed perpendicular to the substrate surface [24] (see Figure 1). The latest studies show that 5 nm diameter nanowires with nano-scale interconnects, and 20 nm vertical nanosheets are manufacturable [25], [26]. Due to their unique channel formation, V-FET circuits do not follow conventional circuit design methodologies.…”

Section: Introductionmentioning

confidence: 99%

“…Considering the manufacturability of advanced nanowire/nanosheet FETs and interconnect structures in the sub-10 nm node[25],[26], we consider our assumptions for the advanced devices and interconnects to be reasonable.VOLUME 4, 2016 …”

mentioning

confidence: 99%

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Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Song

2020

IEEE Access

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The GAAFET (gate-all-around FET) is expected to replace FinFETs in future nodes due to its excellent channel controllability. It is also expected to be an impressive device due to its horizontal or vertical transistor structures. Vertical GAAFETs (V-FETs) are expected to be a promising device compared to horizontal GAAFETs (H-FETs) due to their structure, which allows area reduction and significant parasitic reduction. Besides, V-FETs are positioned on top of each other and thus allow more significant size reductions. Therefore, this paper studies the overall potential of many-tier V-FETs by investigating the essential design factors from the layout perspective. First, we study the factors that should be considered for designing many-tier V-FETs. Second, we propose an interconnect structure that maximizes the advantages of many-tier V-FETs. Third, we compare 2-tier V-FET standard cells to one-tier V-FET cells and visualize the advantages that many-tier V-FET cells provide. Our study shows that 2-tier V-FET standard cells provide a-35.6% area reduction with a cost of +16.5% wirelength and +13.2% parasitic capacitance increase compared to 1-tier V-FET cells. Compared to H-FETs and FinFETs, our cells show-50.1% area reductions with-0.3% wirelength reductions and-18.9% parasitic capacitance reductions. We emphasize that the design freedom to place transistors on top of each other and proper interconnect structures lead to ultra-scale miniaturized standard cell designs. We note that the increase in wirelength and capacitance is due to the vertical size increases and detours that must exist in the designs. Thus, careful circuit design is required to obtain the maximum advantages from V-FETs.

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Section: Interconnect Structure and Circuit Design For Many-tiermentioning

confidence: 83%

Section: Introductionmentioning

confidence: 99%

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Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Song

2020

IEEE Access

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“…In the conventional bottom-up vertical nanowire preparation method, the diameter of the nanowires is mainly controlled by advanced lithography technology [14,21]. Isotropic selective etching of SiGe is a top-down method to obtain nanowires or nanopillars, and its diameter is controlled by etching and does not depend entirely on photolithography [22]. However, how to accurately control the diameter of nanowires or pillars has become a challenging subject.…”

Section: Introductionmentioning

confidence: 99%

“…Then, the method of H 2 O 2 and BOE alternate cycle self-selective etching of SiGe was studied, and the etching accuracy was remarkably improved. However, the surface tension of the wet solution and the capillary effect determine that its application in 3D high aspect ratio devices will be a big limitation in the future [22].…”

Section: Introductionmentioning

confidence: 99%

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Zhou

et al. 2020

Materials

Self Cite

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Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

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Bio‐Inspired 3D Artificial Neuromorphic Circuits

Liu

Wang

et al. 2022

Adv Funct Materials

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Neuromorphic circuits emulating the bio‐brain functionality via artificial devices have achieved a substantial scientific leap in the past decade. However, even with the advent of highly advanced bio‐inspired algorithms, the artificial intelligence based on current neuromorphic circuits is lagging behind significantly when compared with naturally evolved biological neural circuits. This massive and intriguing discrepancy is partly due to the incomprehensive understanding of bio‐brain operating mechanism, which relies heavily on the extremely complexed entangled 3D hierarchical neural networks. Configuring 3D neuromorphic hardware with combined computing and memory functionalities, coupled with compatible progress of software algorithms, can be an inevitable route to surmount the limitation encountered by current 2D artificial circuits. Herein, referring to the neuron configuration in 3D perspective together with detailed signal generation and propagation mechanism, the von Neumann configuration is compared with state‐of‐the‐art in‐memory computing architecture, and the development and perspectives of 3D in‐memory computing neuromorphic circuits are highlighted.

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Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation

Cited by 53 publications

References 16 publications

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Bio‐Inspired 3D Artificial Neuromorphic Circuits

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