Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

Abstract

A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an I on/I off-ratio of 2.1×106 for devices with a diameter of 20 nm. Using a GeSn/Ge-heterostructure with GeSn as the top layer and source of the device, the on-current was increased by ~32%. With these results the high potential of incorporation of GeSn into Ge-MOSFET technology is demonstrated.

Research progress of out-of-plane GeSn nanowires

“…Therefore, a strain-relaxed Ge buffer layer (Ge virtual substrate (VS)) needs to be deposited on the Si substrate as a template for GeSn epitaxy. GeSn NWs are typically grown using the top-down approach in three phase [59][60][61][62][63][64][65]. In the first step, a strain-free Ge buffer layer and GeSn layer are deposited on Si substrate by either CVD mechanism or MBE mechanism, and the Sn content in the GeSn layer determines the Sn content in the GeSn NWs prepared by the top-down method, and thickness of the Ge-VS layer and GeSn layer almost determine the minimum length of out-of-plane vertical GeSn NWs.…”

“…In addition, periodic digital etching, which consists of selflimited O 2 plasma and HF rinse to remove oxide, can further reduce the diameter of NWs precisely [61,64] while minimizing the damage caused by RIE and fabricating GeSn NW with an anisotropic profile and smooth sidewall. The fabrication process of self-assembled GeSn vertical NWs is depicted in figures 2(a)-(c) [62].…”

“…Currently, the application of out-of-plane GeSn NWs is still in the phase of basic research and technology development. However, the literature indicates that out-of-plane GeSn NWs have many potential applications, especially as infrared photodetectors [55,62,91,159,162,[166][167][168], high-efficiency Li-ion battery anodes [122], nanowire SWIR lasers [152,169,170], nanowire transistors (figure 8) [55,60,61,[171][172][173][174][175].…”

“…The main advantages of GAA NW p-FETs are the valence band offset at the Ge 0.92 Sn 0.08 /Ge heterojunction and the low NiGeSn/ GeSn contact resistance. Further, Junk et al have also fabricated smaller diameter (20 nm) vertical GAA NW p-FETs by a top-down method based on Ge and GeSn/Ge heterostructures, with a subthreshold slope of 66 mV dec −1 , a drainbarrier reduction of 35 mV V −1 , and an I ON /I OFF ratio of 2.1 × 10 6 [61]. Emmanuele Galluccio et al reported for the first time some of the key electronic FET performance metrics of nominally undoped, VLS-grown Ge 1-x Sn x such as mobility, I ON /I OFF ratio, subthreshold swing and transconductance (gm) as a function of Sn content (x = 0.03, 0.06 and 0.09) [171].…”