Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths

Yoon, Jun-Sik; Rim, Taiuk; Kim, Jungsik; Meyyappan, M.; Baek, Chang‐Ki; Jeong, Yoon‐Ha

doi:10.1063/1.4895030

Cited by 31 publications

(17 citation statements)

References 15 publications

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“…Gate-all-around (GAA) is a widely-using structure such as logic field-effect transistor (FET) due to its excellent short channel characteristics [1][2][3][4][5][6] or its high surface-to-volume ratio [7,8], 3-D NAND flash memory for bit-cost scalability [9,10], photodiode due to its waveguide effect [11,12], and gas sensor due to its high physical fill factor or surface-to-volume ratio [13,14]. Especially for logic applications, GAAFETs have been introduced by attaining good gate electronics and increasing current drivability under the same active area.…”

Section: Introductionmentioning

confidence: 99%

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Yoon¹,

Jeong²,

Lee³

et al. 2021

Nanowires - Recent Progress

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DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

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Section: Introductionmentioning

confidence: 99%

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Yoon¹,

Jeong²,

Lee³

et al. 2021

Nanowires - Recent Progress

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“…Secondly, we find that source/drain parameter pairs have the opposite directional correlations with PDP, but with very similar sensitivities. Highly-doped source region by reducing parasitic resistance and lightly-doped drain region by decreasing gate-induced drain leakage and improving short channel effects (SCEs) are preferred whenever possible [28]- [30]. For example, L sdj(d) and L sdj(s) are negatively and positively correlated with PDP respectively and these two correlations have similar slopes in fig.13.…”

Section: Correlation and Sensitivity Analysismentioning

confidence: 99%

Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing

et al. 2020

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An optimal design of semiconductor device and its process uniformity are critical factors affecting desired figure-of-merits as well as reducing fabrication cost of fixing possible malfunctioning in semiconductor manufacturing. Two main tasks in optimal device design for semiconductor manufacturing, i.e., parameter optimization and modeling, have been typically used either to characterize the devices by understanding how each parameter affects the device performances or to calibrate the parameters for SPICE circuit simulation. However, there still remains limitations in describing the relationship between all manufacturing parameters and figure-of-merits using several simple equations human experts can utilize. Even with the best model currently available, the optimal design of semiconductor device heavily relies on experiences of human experts and deals with time-consuming ad-hoc trials and non-holistic approaches. In this paper, we propose a new approach for data-based accurate electrical modeling of transistor, which is the most fundamental unit device of semiconductor, and fast optimization of its manufacturing parameters. Instead of the previous analytic approaches, finding finite equations derived from semiconductor physics, we utilize machine learning technique and neural networks to find appropriate modeling functions from data pairs of parameters and figure-of-merits. And for given desired figure-of-merits, we find optimal manufacturing parameters in holistic manner by using the learned functions of neural networks and fast gradient-based optimization method. Experimental results show that our neural-network-based-model directly estimate figure-of-merits with competitive accuracy and that our holistic optimization technique accurately and rapidly adapts the manufacturing parameters to meet desired figure-of-merits.

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“…The gate-all-around nanowire FET is one of the most viable alternatives to current mass produced architectures as it provides an enhanced performance with respect to previous competitors [1] [4]. However it still faces some difficulties to come into market like high production costs and degradation due to variability issues [2] [5].…”

Section: Introductionmentioning

confidence: 99%