Vertical and bevel-structured SiC etching techniques incorporating different gas mixture plasmas for various microelectronic applications

Abstract

This study presents a detailed fabrication method, together with validation, discussion, and analysis, for state-of-the-art silicon carbide (SiC) etching of vertical and bevelled structures by using inductively coupled plasma reactive ion etching (ICP-RIE) for microelectronic applications. Applying different gas mixtures, a maximum bevel angle of 87° (almost vertical), large-angle bevels ranging from 40° to 80°, and small-angel bevels ranging from 7° to 17° were achieved separately using distinct gas mixtures at different ratios. We found that SF6 with additive O2 was effective for vertical etching, with a best etching rate of 3050 Å/min. As for the large-angle bevel structures, BCl3 + N2 gas mixtures show better characteristics, exhibiting a controllable and large etching angle range from 40° to 80° through the adjustment of the mixture ratio. Additionally, a Cl2 + O2 mixture at different ratios is applied to achieve a small-angel bevels ranging from 7° to 17°. A minimum bevel angel of approximately 7° was achieved under the specific volume of 2.4 sccm Cl2 and 3.6 sccm O2. These results can be used to improve performance in various microelectronic applications including MMIC via holes, PIN diodes, Schottky diodes, JFETs’ bevel mesa, and avalanche photodiode fabrication.

High-temperature etching of SiC in SF6/O2 inductively coupled plasma

“…on/in the silicon carbide substrate. As of today, there is a fairly large variety of techniques for the processing of silicon carbide that allow, to some extent, to solve the following problem: wet etching; etching in solvents, stimulated by femtosecond laser; plasma etching; etching in plasma atmospheric discharge; plasma jet processing, and etc [15][16][17][18][19][20][21][22][23][24][25] . The choice of silicon carbide processing method is determined by the specific target, but nevertheless any of the methods must meet a number of general requirements: minimal defect formation on the surface of the etched profile, high etching rates, and high directionality of the processed window during the etching process.…”

“…From the above-listed methods plasma chemical etching (PCE) is one of great interest, which has found wide application in the production of various MEMS and electronic devices for some time now. Wide application of PCE is caused by a high level of process automation and ability to control a large number of process parameters, which allows to optimize the etching process for a specific task and, therefore, provides an opportunity to form various structures of a specific profile 17 . Despite the above-mentioned strengths, there are also certain drawbacks to this method.…”

A Review: Inductively Coupled Plasma Reactive Ion Etching of Silicon Carbide

“…The ICP-RIE etching technology of structures entails the need to produce patterns in the form of vertical, smooth walls forming: holes, deep and narrow trenches or islands [ 23 , 24 ]—the so-called MESA structures (exemplary various etched patterns are shown in Figure 1 ). Etched parts are used, among others, for interconnections and insulation in integrated circuits, diffractive structures in optoelectronic systems, or for creation of complex MEMS.…”

“…It has been observed that the etching rate of a copper mask in SF 6 plasma is the lowest compared to the etching rate of other metallic masks, e.g., aluminum or nickel [ 28 ]. In turn, the nickel mask is better than the chrome mask, as shown by the results of SiC etching in the SF 6 /O 2 plasma [ 23 ]. The selectivity obtained in etching processes with the use of both masks were: 100:1—for SiC with the Ni mask, and 40:1—for SiC with the Cr mask.…”

4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

“…Dry thermal oxidation is performed, and the bottom oxide is etched, as shown in Figure 10e,f. In Figure 10g, a P + polysilicon split gate is deposited on the gate trench, and it is created to the desired length using the RIE-ICP etching process after the etch-back process [34]. Then, oxide is deposited by CVD, and etching is performed to produce a thick bottom oxide, as shown in Figure 10h [35].…”