Verifying fragility in digital systems with uncertainties using DSVerifier v2.0

Abstract

Control-system robustness verification with respect to implementation aspects lacks automated verification approaches for checking stability and performance of uncertain control systems, when considering finite word-length (FWL) effects. Here we describe and evaluate novel verification procedures for digital systems with uncertainties, based on software model checking and satisfiability modulo theories, named as DSVerifier v2.0, which is able to check robust stability of closed-loop control systems with respect to FWL effects. In particular, we describe our verification algorithms to check for limit-cycle oscillations (LCOs), output quantization error, and robust non-fragile stability on common closedloop associations of digital control systems (i.e., series and feedback). DSVerifier v2.0 model checks new properties of closed-loop systems (e.g., LCO), including stability and output quantization error for uncertain plant models, and considers unknown parameters and FWL effects. Experimental results over a large set of benchmarks show that 35%, 34%, and 41% of success can be reached for stability, LCO, and output quantization error verification procedures, respectively, for a set of 396 closed-loop control system implementations and realizations.

QNNVerifier: A Tool for Verifying Neural Networks using SMT-Based Model Checking

“…Furthermore, we let the user customize the fixed-point representation by freely choosing the number of integer and fractional bits. Our approach is based on the fixed-point models in [5]: all arithmetic operations (+, −, * , and /) are modeled as an SMT background theory, thus making them compatible with SMT solvers.…”

Survey on automated symbolic verification and its application for synthesising cyber‐physical systems

“…Indeed, the first two aspects are of extreme relevance in micro‐grids and cyber‐physical systems, in order to ensure reliability, which is a key issue for (smart) cities, industries, and consumers, and the third one is essential in systems that implement device models, such as digital filters and controllers, which present a behaviour that is highly dependent on signal inputs and outputs and whose deployment may be heavily affected by hardware restrictions. In that sense, as already mentioned, DSVerifier [70, 104] is a powerful tool, which has been evolved and now is capable of checking many properties in digital systems, including digital filters, digital controllers, and closed‐loop systems [191], while taking into account fragility aspects (e.g. FWL problems).…”

Formal synthesis of non-fragile state-feedback digital controllers considering performance requirements for step response

“…It is an approach that determines unknown parameters inside partial programs so that the resulting elements satisfy correctness properties 13 . Some studies have been done using CEGIS for performing synthesis 14 and such a work can be successfully used for designing stable controllers for continuous plants; however, when FWL effects are considered, a further verification step should then be performed, given the possibility of overflow, LCO, and instability, for instance 15 . Indeed, it suggests that an additional verification phase could be integrated into the mentioned CEGIS approach and then used to generate elements already suitable for a given FWL scenario.…”