Verifying distributed directory-based cache coherence protocols: S3.mp, a case study

Pong, Fong; Nowatzyk, Andreas; Aybay, Gunes; Dubois, Michel

doi:10.1007/bfb0020472

Cited by 18 publications

(15 citation statements)

References 12 publications

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“…Verification based on M r is at least as accurate as verification runs based on M for the detection of data inconsistencies. Importantly, since M r is independent of the system size, the verification of M r could discover protocol errors that may go undetected in M with a small number of processors [22].…”

Section: Discussionmentioning

confidence: 99%

“…Therefore, the SSM model must distinguish the case of null copy in the "shared" state from the case of at least one or multiple. Other examples include the Illinois protocol, the Firefly protocol [3,21] and the S3.mp protocol [22] which all have transitions sensitive to the number of caches in a particular state.…”

Section: Discussionmentioning

confidence: 99%

“…In SSM repetition constructors are used to represent global states [21][22][23]. In this paper we will use the following set of constructors:…”

Section: Abstract State Representationmentioning

confidence: 99%

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Formal automatic verification of cache coherence in multiprocessors with relaxed memory models

Pong

Dubois

2000

IEEE Trans. Parallel Distrib. Syst.

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Shared-MemoryMultiprocessor, relaxed memory consistency models, delayed consistency, verification, symbolic state model State-based, formal methods have been successfully applied to the automatic verification of cache coherence in sequentially c onsistent systems. However, coherence in shared-memory multiprocessors under a relaxed memory model is much more complex to verify automatically. With relaxed memory models, incoming invalidations and outgoing updates can be delayed in each cache while processors are allowed to race ahead. This buffering of memory accesses considerably increases the amount of state in each cache and the complexity of protocol interactions. Moreover, because caches can hold inconsistent copies of the same data for long periods of time, coherence cannot be verified by simply checking that cached copies are identical at all times. This paper makes two major contributions. First, we demonstrate how to model and verify cache coherence under a relaxed memory model in the context of state-based verification methods. Frameworks for modeling the hardware and for generating correct memory access sequences driving the hardware model are developed. We also show correctness properties which must be verified on the hardware model. Second, we demonstrate a successful application of a state-based verification tool called SSM for the verification of delayed protocol, an aggressive protocol for relaxed memory models. SSM is based on an abstraction technique preserving the properties to verify. We show that with classical, explicit approaches the verification of cache coherence is realistically unfeasible because of the state space explosion problem whereas SSM is able to verify protocols both at both behavioral and message-passing levels.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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Formal automatic verification of cache coherence in multiprocessors with relaxed memory models

Pong

Dubois

2000

IEEE Trans. Parallel Distrib. Syst.

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“…For checking data consistency, we only model one cache block of one memory location. Replacement of the block is modeled by assuming that it can happen at any time [13], [14]. The home node of the block is distinguished from other homogeneous remote nodes.…”

Section: Model and Correctness Propertiesmentioning

confidence: 99%

Design verification of the S3.mp cache-coherent shared-memory system

Pong

Browne²,

Nowatzyk

et al. 1998

IEEE Trans. Comput.

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Abstract-This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable Shared-memory MultiProcessor (S3.mp) at three levels of abstraction: the memory consistency model, the cache coherence protocol, and the implementation.Index Terms-Cache-coherent shared-memory multiprocessors, distributed directory-based protocols, formal verification, debugging.

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“…One of the most successful application domains for model checking has been multiprocessor cache coherence protocols (e.g., [17,10,6,8,15,23,24,3,20,14] are some early works). The application domain is commercially very important, since almost all high-end servers are now cache-coherent multiprocessors; the protocols are tricky, highly concurrent, and hence bug-prone; and the protocols can be modeled in finite state, naturally supporting model checking.…”

Section: Introductionmentioning

confidence: 99%