Verification of Physical Chip Layouts Using GDSII Design Data

Singla, A.; Lippmann, Bernhard; Graeb, Helmut

doi:10.1109/ivsw.2019.8854432

“…For the ensuing comparison, the heavily nested GDSII file is parsed into the same polygon format. This can be done through the algorithms by Singla et al [23]. Initially, both layers cannot be compared: they are completely un-aligned regarding scale, rotation, and translation.…”

Section: Methodology -The Vital Frameworkmentioning

confidence: 99%

ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering

Ludwig¹,

Bette²,

Lippmann³

2022

Preprint

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The semiconductor industry is heavily relying on outsourcing of design, fabrication, and testing to third parties. The threat of possibly malicious actors in this ramified supply-chain poses a risk for the integrity of integrated circuits (ICs) and hardware Trojans (HTs) are a heavily discussed topic in academia and the industry. A variety of pre- and post-silicon HT prevention and detection techniques has been suggested in prior works. Hardware reverse engineering has the potential to detect potential modification in physical layouts. Yet, there is no model to qualitatively and quantitatively rate the complex and expensive reverse engineering (RE) process addressing its inherent process aberrations and consequently provide a tool for layout verification. The ViTaL framework introduces a statistical validation technique, based on physical layout verification through RE and considers all potential sources of errors. The golden-model based framework is technology-agnostic, scaleable, and user input is optional. For the first time, results of fine pitch metallization layers of a CMOS 40nm process node IC are presented quantitatively and the limitations and possibilities are discussed.<br>

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“…The semiconductor industry global supply chain has created the enormous challenge of providing authentic, trusted microelectronics devices, a concern for both industry and government alike [1]. The untrusted foundry threat is not mitigated through cursory device electrical testing, requiring a much more robust and invasive analysis of the fabricated part and comparison to the golden design files for a high quantitative level of trust in a device through a cooperative Verification and Validation (V&V) workflow [2,3]. While the V&V workflow demands a considerable amount of time, a diverse expertise in manpower, and a wide array of tools and facilities for execution, it can fully verify that a part is physically and functionally identical to the original design with a high degree of confidence.…”

Section: Introductionmentioning

confidence: 99%

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

Waite¹,

Patel²,

Kelley³

et al. 2021

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This paper presents the first design reconstruction on the Front-End-of-Line and Middle-of-Line layers of a 14 nm node FinFET design. To accomplish this, a large region of interest within a custom designed 14 nm node ASIC device was delayered, imaged, and analyzed to reconstruct the GDSII design file and verify a 100% match to the golden GDSII design. This work leveraged previous developments in each stage of the front half of the cooperative Verification and Validation (V&V) workflow combined with new techniques and processes developed for processing 3D architecture FET devices. We have demonstrated the critical first step to performing a full V&V workflow on an advanced technology node device, starting from the fabricated silicon device to the design extraction. The process development knowledge gained while reaching this milestone will further accelerate future advancements toward providing trusted advanced technology node devices in a timely manner. <br>

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“…The semiconductor industry global supply chain has created the enormous challenge of providing authentic, trusted microelectronics devices, a concern for both industry and government alike [1]. The untrusted foundry threat is not mitigated through cursory device electrical testing, requiring a much more robust and invasive analysis of the fabricated part and comparison to the golden design files for a high quantitative level of trust in a device through a cooperative Verification and Validation (V&V) workflow [2,3]. While the V&V workflow demands a considerable amount of time, a diverse expertise in manpower, and a wide array of tools and facilities for execution, it can fully verify that a part is physically and functionally identical to the original design with a high degree of confidence.…”

Section: Introductionmentioning

confidence: 99%

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

Waite¹,

Patel²,

Kelley³

et al. 2021

Preprint

0

View full text Add to dashboard Cite

This paper presents the first design reconstruction on the Front-End-of-Line and Middle-of-Line layers of a 14 nm node FinFET design. To accomplish this, a large region of interest within a custom designed 14 nm node ASIC device was delayered, imaged, and analyzed to reconstruct the GDSII design file and verify a 100% match to the golden GDSII design. This work leveraged previous developments in each stage of the front half of the cooperative Verification and Validation (V&V) workflow combined with new techniques and processes developed for processing 3D architecture FET devices. We have demonstrated the critical first step to performing a full V&V workflow on an advanced technology node device, starting from the fabricated silicon device to the design extraction. The process development knowledge gained while reaching this milestone will further accelerate future advancements toward providing trusted advanced technology node devices in a timely manner. <br>

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Verification of Physical Chip Layouts Using GDSII Design Data

Cited by 11 publications

References 6 publications

ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering

ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

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