Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

Jerdonek, R.T.; Bandy, W.R.

doi:10.1109/t-ed.1978.19198

Cited by 9 publications

(3 citation statements)

References 2 publications

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“…Theoretical calculations by Kranzer and Fichtner 186 indicate that similar subthreshold characteristics should occur when the silicon film thickness (X s ) is greater than the maximum depletion layer width (X d ). 46 ' 52 Jerdonek and Brandy 189 have investigated the electron velocity saturation in NMOS-SOS deep depletion transistors. The important parameters, therefore, appear to be film thickness and fast states at the silicon-sapphire interface.…”

Section: Time (/Xsec)mentioning

confidence: 99%

The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

Ipri

1981

Silicon Integrated Circuits

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Section: Time (/Xsec)mentioning

confidence: 99%

The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

Ipri

1981

Silicon Integrated Circuits

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“…This condition can never be reached because of the contribution of diffusion to the current flow. We therefore note that under all square root signs in (10) we will have positive quantities and also that the voltage term is generally much larger than the term l'. We may therefore make expansions of all square root quantities, and by retaining terms to the first order, we obtain…”

Section: (Loc)mentioning

confidence: 92%

Velocity-Saturated Characteristics of Short-Channel MOSFETs

Taylor

1984

At&T Bell Laboratories Technical Journal

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A theory is developed for the I-V characteristics of metal oxide semiconductor field-effect transistors (MOSFETs) when the channel fields are sufficiently high to cause appreciable saturation of the carrier drift velocity. The full velocity-field curve for bulk silicon is used with the base value adjusted to account for surface scattering effects. Use of this form gave the best fit to experimental data. Using some simple expansions to reduce the rather complex integral produces a useful analytic result, which gives a continuous description from the square law results for long-channel devices throughout the whole range of velocity-saturated operation in short-channel devices. For the first time the electron temperature has been introduced as the parameter, which increases the channel charge at pinch-off, decreases the saturation voltage, and increases the channel field at the pinch-off point as the current (and hence bias voltages) is increased. The effects of series resistance and surface roughness scattering are incorporated into the analytic formulation. We compare the results with experimental submicron devices and find excellent agreement.

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“…The typical V p lowering phenomenon should be due to velocity saturation in metal-oxide-semiconductor fieldeffect transistors (MOSFETs). [17][18][19][20][21] Carrier velocity saturates through the interaction with optical phonons under a high drain-to-source electric field prior to depletion in the drain region. Velocity saturation appears in the case of shortchannel devices including poly-Si TFTs 22) under a high drain-to-source electric field.…”

Section: Remarks On Similar Phenomenamentioning

confidence: 99%

Pinch-Off Voltage Lowering in Polycrystalline Silicon Thin-Film Transistors

Ikeda

Sano

2011

Jpn. J. Appl. Phys.

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Pinch-off voltage (V p) lowering phenomenon in the output characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported and investigated by measurement and device simulation. As the trap density increases, the observed V p becomes smaller than the ideal V p while maintaining a linear relationship with the gate–source voltage (V gs). The device simulation analysis revealed two mechanisms for V p lowering. One is current saturation due to the increase in onset gate–drain voltage (V gd), causing the drain region to become highly resistive, which originates from the gradual increase in surface potential with V gs. This is interpreted as an expansion of the conventional pinch-off concept. The other is the current limitation, controlled by grain boundary (GB) and intragrain conductance at the drain edge, which is peculiar to poly-Si TFTs. On the basis of the above analysis, a GB-conductance-limited carrier transport model is proposed. Its good agreement with the measurements suggests the suitability of this model for describing V p lowering.

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Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

Cited by 9 publications

References 2 publications

The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

Velocity-Saturated Characteristics of Short-Channel MOSFETs

Pinch-Off Voltage Lowering in Polycrystalline Silicon Thin-Film Transistors

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