Vectorization of Hybrid Breadth First Search on the Intel Xeon Phi

Paredes, Mireya; Riley, Graham; Luján, Mikel

doi:10.1145/3075564.3075573

Cited by 3 publications

(11 citation statements)

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“…However, little detail of their implementation is provided, so in this paper we present the details of the vectorisation of both approaches involved in the hybrid BFS algorithm, top-down and bottom-up. The performance of our hybrid BFS algorithm [2] is better compared with those in Gao et al in [9].…”

Section: Related Workmentioning

confidence: 71%

“…The key contribution of this work builds on the studies carried out by Gao et al in [7] and [9]. In the first study [7], they present the vectorisation of the top-down BFS algorithm using vector intrinsic functions, which was outperformed by Paredes et al [3], clarifying the impact of prefetching, thread affinity and the usage rate of the vector unit. Gao et al's second study [9] is related to the vectorisation of the hybrid BFS algorithm.…”

Section: Related Workmentioning

confidence: 96%

“…In addition, we show results of a direct port to a more recent version of the Xeon Phi (Knights Landing (KNL) and a Skylake CPU which supports most of the AVX-512 instruction set that our algorithms exploit. A novel optimised parallel version of the hybrid BFS is presented using vectorisation [2], building on top of the vectorised top-down BFS introduced by Paredes et al [3]. The concept of the hybrid BFS algorithm was introduced by Beamer et al [4], which consists of a combination of the top-down and the bottom-up BFS algoritms.…”

Section: Introductionmentioning

confidence: 99%

“…The introduction of the hybrid BFS algorithm is presented in Section 5. This algorithm is composed of two approaches that traverse the graph in two different directions: top-down and bottom-up, the description of the parallelisation of both approaches using vectorisation is presented in Sections 6, which includes a brief review of [3], and Section 7, respectively. Sections 3, 4 and 5 are essentially background.…”

Section: Introductionmentioning

confidence: 99%

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Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi

Paredes

Riley

Luján

2020

IEEE Trans. Parallel Distrib. Syst.

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Modern applications generate massive amounts of data that is challenging to process or analyse. Graph algorithms have emerged as a solution for the analysis of such data because they can represent the entities participating in the generation of large-scale datasets in terms of vertices and their relationships in terms of edges. Graph analysis algorithms are used for finding patterns within these relationships, aiming to extract information to be further analysed. The breadth-first search (BFS) is one of the main graph search algorithms used for graph analysis and its optimisation has been widely researched using different parallel computers. However, the parallelisation of BFS has been shown to be challenging because of its inherent characteristics, including irregular memory access patterns, data dependencies and workload imbalance, that limit its scalability. This paper investigates the optimisation of the BFS on the Xeon Phi (Knights Corner), a modern parallel architecture provided with an advanced vector processor supporting the AVX-512 instruction set, using a bespoke development framework integrated with the Graph 500 benchmark. In addition, to demonstrate portability, we show results for a direct port of the algorithms to a more recent version of the Xeon Phi (Knights Landing) and to a Skylake CPU which supports most of the AVX-512 instruction set. Optimised parallel versions of two high-level algorithms for BFS were created using vectorisation, starting with the conventional top-down BFS algorithm and, building on this, a hybrid BFS algorithm. On the KNC our best implementations result in speedups of 1.37x (top-down) and 1.37x (hybrid), for a one million vertices graph, compared to the state-of-the-art. On the KNL and Skylake, the performance is higher than on KNC. In addition, we show results of our best hybrid algorithm on real-world graphs from the SNAP datasets with speedups up to 1.3x on KNC. Performance on KNL and Skylake is again higher, demonstrating the robustness and portability of our algorithm. The hybrid BFS algorithm can be further used to speed up other graph analysis algorithms and the lessons learned from vectorisation can be applied to other algorithms targeting existing and future models of the Xeon Phi and other advanced vector architectures.

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Section: Related Workmentioning

confidence: 71%

Section: Related Workmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi

Paredes

Riley

Luján

2020

IEEE Trans. Parallel Distrib. Syst.

Self Cite

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“…Multiple studies showcase KNL-specific performanceengineering techniques, successfully applied to scientific applications, from molecular dynamics simulations [65] to seismic simulations [66]. Applying similar techniques to graphprocessing kernels leads to significantly lower performance gain [67], due to inherent features of graph processing workloads (see Section III). Our optimization strategies are less intrusive, as we approach the performance analysis and tuning problem from the perspective of a regular, non-expert user.…”

Section: Related Workmentioning

confidence: 99%

Exploring HPC and Big Data Convergence: A Graph Processing Study on Intel Knights Landing

Uta

Vărbănescu

Musaafir

et al. 2018

2018 IEEE International Conference on Cluster Computing (CLUSTER)

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The question "Can big data and HPC infrastructure converge?" has important implications for many operators and clients of modern computing. However, answering it is challenging. The hardware is currently different, and fast evolving: big data uses machines with modest numbers of fat cores per socket, large caches, and much memory, whereas HPC uses machines with larger numbers of (thinner) cores, non-trivial NUMA architectures, and fast interconnects. In this work, we investigate the convergence of big data and HPC infrastructure for one of the most challenging application domains, the highly irregular graph processing. We contrast through a systematic, experimental study of over 300,000 core-hours the performance of a modern multicore, Intel Knights Landing (KNL) and of traditional big data hardware, in processing representative graph workloads using state-of-the-art graph analytics platforms. The experimental results indicate KNL is convergence-ready, performance-wise, but only after extensive and expert-level tuning of software and hardware parameters.

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