Vector–Logic Synthesis of Deductive Matrices for Fault Simulation

Abstract

The main idea is to create vector-logic computing that uses only read-write transactions on address memory to process large data. The main task is to implement new simple and reliable models and methods of vector computing based on primitive read-write transactions in the technology of vector flexible interpretive simulation of digital system faults. Vector-logic computing is a computational process based on read-write transactions over bits of a binary vector of functionality, where the input data is the addresses of the bits. A vector method for the synthesis of deductive matrices for transporting input fault lists is proposed, which has a quadratic computational complexity. The method is a development of the deductive vector synthesis algorithm based on the truth table. The deductive matrix is intended for the synthesis and verification of tests using parallel simulation of faults, as addresses, based on a read-write transaction of deductive vector cells in memory.