Vector instruction set support for conditional operations

Smith, J.E.; Faanes, G.; Sugumar, R.

doi:10.1109/isca.2000.854396

Cited by 8 publications

(11 citation statements)

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“…The idea of masking was extended to software optimizations along with the idea of exchanging control flow for data flow with the concept of predicated execution [1]. In the context of vectors, Smith et al [27] proposed densitytime execution, which is similar to compaction but operates in time on traditional masked vector execution. Smith et al also provide a good summary of performance comparisons among various vector ISAs that incorporate conditional operations.…”

Section: Related Workmentioning

confidence: 99%

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Rhu¹,

Erez²

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Wide SIMD-based GPUs have evolved into a promising platform for running general purpose workloads. Current programmable GPUs allow even code with irregular control to execute well on their SIMD pipelines. To do this, each SIMD lane is considered to execute a logical thread where hardware ensures that control flow is accurate by automatically applying masked execution. The masked execution, however, often degrades performance because the issue slots of masked lanes are wasted. This degradation can be mitigated by dynamically compacting multiple unmasked threads into a single SIMD unit. This paper proposes a fundamentally new approach to branch compaction that avoids the unnecessary synchronization required by previous techniques and that only stalls threads that are likely to benefit from compaction. Our technique is based on the compaction-adequacy predictor (CAPRI). CAPRI dynamically identifies the compactioneffectiveness of a branch and only stalls threads that are predicted to benefit from compaction. We utilize a simple single-level branch-predictor inspired structure and show that this simple configuration attains a prediction accuracy of 99.8% and 86.6% for non-divergent and divergent workloads, respectively. Our performance evaluation demonstrates that CAPRI consistently outperforms both the baseline design that never attempts compaction and prior work that stalls upon all divergent branches.

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Section: Related Workmentioning

confidence: 99%

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Rhu¹,

Erez²

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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“…The compiler statically encodes this information by emitting vop4 under no predicate condition. Several optimizations such as density-time execution and compress-expand transformations have been proposed [33] and evaluated [14] to save execution time of sparsely activated vector instructions. However, these optimizations cannot prevent vector instructions with an all-false predicate mask from being fetched and decoded.…”

Section: A Vector Machinesmentioning

confidence: 99%

“…The Intel MIC has 8 explicit vector predicate registers [11] while the Cray-1 has one vector predicate register on which vector instructions are implicitly predicated [29,33]. AMD GPUs use special vcc and exec predicate registers to hold vector comparison results and to implicitly mask instruction execution [2].…”

Section: A Vector Machinesmentioning

confidence: 99%

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Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Lee

Grover²,

Krashinsky³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Data-parallel architectures must provide efficient support for complex control-flow constructs to support sophisticated applications coded in modern single-program multipledata languages. As these architectures have wide datapaths that process a single instruction across parallel threads, a mechanism is needed to track and sequence threads as they traverse potentially divergent control paths through the program. The design space for divergence management ranges from softwareonly approaches where divergence is explicitly managed by the compiler, to hardware solutions where divergence is managed implicitly by the microarchitecture. In this paper, we explore this space and propose a new predication-based approach for handling control-flow structures in data-parallel architectures. Unlike prior predication algorithms, our new compiler analyses and hardware instructions consider the commonality of predication conditions across threads to improve efficiency. We prototype our algorithms in a production compiler and evaluate the tradeoffs between software and hardware divergence management on current GPU silicon. We show that our compiler algorithms make a predication-only architecture competitive in performance to one with hardware support for tracking divergence.

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“…Their scope is limited to the vectorization of dot-products (reductions) and FFTs, which makes them regular and simple to implement. Finally, VIRAM supports conditional execution of element operations for virtually all vector instructions using the flag registers as sources of element masks [21].…”

Section: Instruction Set Overviewmentioning

confidence: 99%

Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

Kozyrakis¹,

Patterson²

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.

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Vector instruction set support for conditional operations

Cited by 8 publications

References 0 publications

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

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