Vector Extensions for Decision Support DBMS Acceleration

Hayes, Timothy; Palomar, Oscar; Unsal, Osman S.; Cristal, Adrián; Valero, Mateo

doi:10.1109/micro.2012.24

Cited by 29 publications

(38 citation statements)

References 27 publications

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“…We find that hash table lookups account for nearly all of the indexing time, corroborating earlier research [16]. Figure 2b shows the normalized hash table lookup time, broken down into its primitive operations: key hashing (Hash) and node list traversal (Walk).…”

Section: Profiling Analysis Of a Modern Dbmssupporting

confidence: 84%

“…In practice; however, the sequential nature of an individual hash index lookup, composed of key hashing followed by pointer chasing through a list of nodes, results in significant time constants even in highly tuned in-memory DBMSs. Consequently, a recent study of data analytics on a state-of-the-art commercial DBMS found that 41% of the total execution time for a set of TPC-H queries goes to hash index lookups used in hash-join operations [16].…”

Section: Introductionmentioning

confidence: 99%

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Meet the walkers

Kocberber¹,

Grot

Picorel³

et al. 2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

150

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The explosive growth in digital data and its growing role in real-time decision support motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance and ushered an era of power-limited chips. These developments motivate the design of DBMS accelerators that (a) maximize utility by accelerating the dominant operations, and (b) provide flexibility in the choice of DBMS, data layout, and data types.We study data analytics workloads on contemporary inmemory databases and find hash index lookups to be the largest single contributor to the overall execution time. The critical path in hash index lookups consists of ALU-intensive key hashing followed by pointer chasing through a node list. Based on these observations, we introduce Widx, an on-chip accelerator for database hash index lookups, which achieves both high performance and flexibility by (1) decoupling key hashing from the list traversal, and (2) processing multiple keys in parallel on a set of programmable walker units. Widx reduces design cost and complexity through its tight integration with a conventional core, thus eliminating the need for a dedicated TLB and cache. An evaluation of Widx on a set of modern data analytics workloads (TPC-H, TPC-DS) using full-system simulation shows an average speedup of 3.1x over an aggressive OoO core on bulk hash table operations, while reducing the OoO core energy by 83%.

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Section: Profiling Analysis Of a Modern Dbmssupporting

confidence: 84%

Section: Introductionmentioning

confidence: 99%

Meet the walkers

Kocberber¹,

Grot

Picorel³

et al. 2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

150

View full text Add to dashboard Cite

show abstract

“…These parameters were shown to be reasonable in recent vector work [8], [11]. They also represent a configuration that we anticipate could eventually appear on the market given current trends.…”

Section: A Query and Input Datasupporting

confidence: 59%

“…By default, PTLsim uses a fixed latency memory system that does not model bandwidth and contention issues. Recent work on vector processors [11] has shown that they have the ability to saturate a system's available bandwidth, thus making it crucial to model the memory system accurately when executing vectorised algorithms, otherwise the results may be inaccurate and misleading. For this reason, we have integrated DRAMSim2 [12]-a cycle-accurate memory system simulator-into PTLsim and replaced the default memory model.…”

Section: Simulation Frameworkmentioning

confidence: 99%

Future vector microprocessor extensions for data aggregations

Hayes

Palomar

Ünsal

et al. 2016

SIGARCH Comput. Archit. News

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Abstract-As the rate of annual data generation grows exponentially, there is a demand to aggregate and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. Today, Dennard scaling has ceased and further performance must come from exploiting parallelism. Single instruction-multiple data (SIMD) instruction sets offer a highly efficient and scalable way of exploiting data-level parallelism (DLP). While microprocessors originally offered very simple SIMD support targeted at multimedia applications, these extensions have been growing both in width and functionality. Observing this trend, we use a simulation framework to model future SIMD support and then propose and evaluate five different ways of vectorising data aggregation. We find that although data aggregation is abundant in DLP, it is often too irregular to be expressed efficiently using typical SIMD instructions. Based on this observation, we propose a set of novel algorithms and SIMD instructions to better capture this irregular DLP. Furthermore, we discover that the best algorithm is highly dependent on the characteristics of the input. Our proposed solution can dynamically choose the optimal algorithm in the majority of cases and achieves speedups between 2.7× and 7.6× over a scalar baseline.

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“…One of the most time-consuming query operations is the table join. Previous studies have demonstrated that table joins can account for more than 40% of total execution time [1]. The hash join consists of a build phase using the smaller table to make the hash table and a probe phase where all keys in the larger table are probed against the hash table for matches. …”

Section: Introductionmentioning

confidence: 99%

HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA

Salami

Arcas-Abella

Sönmez

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-In this paper we present HATCH, a novel hash join engine. We follow a new design point which enables us to effectively cache the hash table entries in fast BRAM resources, meanwhile supporting collision resolution in hardware. HATCH enables us to have the best of two worlds: (i) to use the full capacity of the DDR memory to store complete hash tables, and (ii) by employing a cache, to exploit the high access speed of BRAMs. We demonstrate the usefulness of our approach by running hash join operations from 5 TPC-H benchmark queries and report speedups up to 2.8x over a pipeline-optimized baseline.

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Vector Extensions for Decision Support DBMS Acceleration

Cited by 29 publications

References 27 publications

Meet the walkers

Meet the walkers

Future vector microprocessor extensions for data aggregations

HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA

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