VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches

Khatamifard, S. Karen; Resch, Michael; Kim, Nam Sung; Karpuzcu, Ulya R.

doi:10.1109/iccd.2016.7753353

Cited by 14 publications

(10 citation statements)

References 15 publications

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“…To model PV for FinFET technology at STC and NTC operating conditions, the VAR-IUS [7], VARIUS-NTV [8] and VARIUS-TC [22] models have been incorporated. Feeding an in-house statistical timing analysis tool with the architectural metadata from Multi2Sim and synthesized ALU netlist, the sensitized delay characteristics of several FUs have been obtained.…”

Section: Methodsmentioning

confidence: 99%

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Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis

Sanyal

Basu

Bal

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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General-purpose graphics processing units (GPGPU), owing to their enormous parallelism have found ubiquitous applications in parallel computing. Along with an unprecedented performance offered by every new generation of the GPGPUs, their peak power rating has also increased over the years. As an inevitable consequence, Near-Threshold Computing (NTC) has come to the rescue, offering a substantially lower demand on the power supply unit, while striving to achieve a super-threshold performance, by exploiting a higher parallelism. However, a severe device-level delay variability arising from process variation (PV), can significantly diminish the NTC system performance. In this work, choke points-a unique device-level characteristic of PV at NTC-that can exacerbate the delays of the GPGPU parallel warps have been explored. In order to improve the NTC GPU performance, a family of holistic circuit-architectural solutions, referred to as Choke Point Aware Warp Speculator (CPAWS) has been proposed. CPAWS identifies the choke point induced critical warps in GPGPU applications, and improves their execution latencies in their respective execution units. Compared to a state-of-the-art warp scheduling policy, the best scheme improves the performance and energy-efficiency of an NTC GPU by ∼39% and ∼31%, respectively. while incurring marginal hardware overheads.

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Section: Methodsmentioning

confidence: 99%

“…The impact of the within-die PV for STC and NTC operating conditions is incorporated by using the VARIUS [7] and VARIUS-NTV [8] models. The FinFET characteristics are obtained using the VARIUS-TC model [22].…”

Section: Device Layermentioning

confidence: 99%

Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis

Sanyal

Basu

Bal

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…They also produced energy and power factors as well. Khatamifard et al 17 proposed a modular architecture-level model of parametric variation to characterize variation-incurred unpredictability at an early design stage. This paper examines the case of FinFETs in particular.…”

Section: Related Workmentioning

confidence: 99%

“…The variation of the transistor dimensions impacts the concentration of dopants as well, which also affects the threshold voltage. 17 Process variation is usually captured by the threshold voltage, the gate length, and the fin height. 17 26 For every mentioned parameter, the impact of process variation is estimated using two components: systematic and random.…”

Section: Process Variation Modellingmentioning

confidence: 99%

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System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Majzoub¹,

Taouil²,

Hamdioui³

2019

Journal of Low Power Electronics

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Standard low power design utilizes a variety of approaches for supply and threshold control to reduce dynamic and idle power. At a very early stage of the design cycle, the V dd and V th values are estimated, based on the power budget, and then used to scale the delay and estimate the design performance. Furthermore, process variation in sub-20 nm feature technologies introduces a substantial impact on speed and power. Thus, the impact of such variation on the scaled delay has to also be considered in the performance estimation. In this paper, we propose a system-level model to estimate this delay, taking into consideration voltage scaling under within-die process variation for both planar and FinFET CMOS transistors in the sub-20 nm regime. The model is simple, has acceptable accuracy and is particularly useful for architectural-level simulations for lowpower design exploration at an early stage in the design space exploration. The proposed model estimates the delay in different supply voltage and threshold voltage ranges. The model uses a modified alpha-power equation to measure the delay of the critical path of a computational logic core. The targeted technology nodes are 14 nm, 10 nm, and 7 nm for FinFETs, and 22 nm, and 16 nm for planar CMOS. Within-die process variation is assumed to be lumped in with the threshold voltage and the transistor channel length and width to simplify its impact on delay. For the given technology nodes, the average percentage error numbers of theproposed delay equation compared to hSpice are between 0.5% to 14%.

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DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

2020

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The ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an effective way to improve the energy efficiency of register files. However, at these operating voltages, the reliability of the circuit is compromised. This work aims to tolerate permanent faults from process variations in large GPU register files operating below the safe supply voltage limit. To do so, this paper proposes a microarchitectural patching technique, DC-Patch, exploiting the inherent data redundancy of applications to compress registers at run-time with neither compiler assistance nor instruction set modifications. Instead of disabling an entire faulty register file entry, DC-Patch leverages the reliable cells within a faulty entry to store compressed register values. Experimental results show that, with more than a third of faulty register entries, DC-Patch ensures a reliable operation of the register file and reduces the energy consumption by 47% with respect to a conventional register file working at nominal supply voltage. The energy savings are 21% compared to a voltage noise smoothing scheme operating at the safe supply voltage limit. These benefits are obtained with less than 2 and 6% impact on the system performance and area, respectively.

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VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches

Cited by 14 publications

References 15 publications

Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis

Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

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