Variation-Tolerant, Power-Safe Pattern Generation

Devanathan, V. R.; Ravikumar, C.P.; Kamakoti, V.

doi:10.1109/mdt.2007.118

Cited by 8 publications

(18 citation statements)

References 11 publications

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“…The impact of process variation on delay fault testing of ICs has recently received increased attention [147,143,148,149,150,151]. Process variation tends to affect gate-delay and subsequently path-delay and can change the ratio between rise-time and fall-time for a gate.…”

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

“…Another problem in delay fault testing under process variation is that some process variation induced delay is accentuated by IR-drop (fluctuations in supply voltage) and causes false delay test failures [143]. The study in [150] presented variation-tolerant delay fault test generation, to avoid false delay test failures, by minimising the switching activity due to the transitions that are caused by the delay fault test. The reasoning behind the approach in [150] is that switching activity causes IR-drop.…”

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

“…The study in [150] presented variation-tolerant delay fault test generation, to avoid false delay test failures, by minimising the switching activity due to the transitions that are caused by the delay fault test. The reasoning behind the approach in [150] is that switching activity causes IR-drop. By limiting the switching activity due to the delay fault test, process variation induced delay will lead to less false delay test failures.…”

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

“…Research has shown that various defects have supply voltagedependent behaviour and some are better detected at a low supply voltage whereas others are better detected at an elevated supply voltage (Table 2.1). Recent research on process variation has addressed problems in delay fault testing [147,143,148,149,150,151] and there is interest in logic testing under process variation as well [99]. This progress is encouraging, however more research is needed to gain better understanding, with the aim to develop low-cost and effective test solutions for designs with multiple supply voltages and ICs that are influenced by process variation.…”

Section: Motivationmentioning

confidence: 99%

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Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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The final part studies the impact of process variation on the behaviour of bridge defects.Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation.

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Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

Section: Delay Fault Testing Under Process Variationmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

See 2 more Smart Citations

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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“…Recent research has reported that process variation has an impact on manufacturing test quality. The work in [3]- [6] considered the effect of process variation on at-speed and delay test, addressing the issues of calculating delay as a function of process variables [5], identification of the longest path [3], [6] and calculation of a test response capture time that tolerates variation [4]. This paper addresses the impact of process variation on static defects with focus on resistive bridging faults.…”

Section: Introductionmentioning

confidence: 99%

Process Variation-Aware Test for Resistive Bridges

Ingelsson

Al-Hashimi

Khursheed

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesised ISCAS benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation.

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Distribution of defect clusters in the primary damage of ion irradiated 3C-SiC

Liu

Szlufarska

2018

Journal of Nuclear Materials

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We report a statistical analysis of sizes and compositions of clusters produced in cascades during irradiation of SiC. The results are obtained using molecular dynamics (MD) simulations of cascades caused by primary knock-on atoms (PKAs) with energies between 10 eV and 50 keV. The results are averaged over six crystallographic directions of the PKA and integrated over PKA energy spectrum derived from the Stopping and Range of Ions in Matter (SRIM) code. Specific results are presented for 1 MeV Kr ion as an example of an impinging particle. We find that distributions of cluster size n for both vacancies and interstitials obey a power law = % and these clusters are dominated by carbons defects. The fitted values of A and S are different than values reported for metals, which can be explained through different defect energetics and cascade morphology between the two classes of materials. In SiC, the average carbon ratio for interstitial clusters is 91.5%, which is higher than the ratio of C in vacancy clusters, which is 85.3%. Size and composition distribution of in-cascade clusters provide a critical input for long-term defect evolution models. Keywordssilicon carbide, intra-cascade clusters, size distribution, cluster composition discussed in detail in Ref. [36] and are carried out using the Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS) [44] package.

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Variation-Tolerant, Power-Safe Pattern Generation

Cited by 8 publications

References 11 publications

Investigation into voltage and process variation-aware manufacturing test

Investigation into voltage and process variation-aware manufacturing test

Process Variation-Aware Test for Resistive Bridges

Distribution of defect clusters in the primary damage of ion irradiated 3C-SiC

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