2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition 2009
DOI: 10.1109/date.2009.5090648
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Variation resilient adaptive controller for subthreshold circuits

Abstract: Abstract-Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for powerlimited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurat… Show more

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Cited by 6 publications
(2 citation statements)
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“…Body-biasing has also been proposed to mitigate the impact of variations [13]. A controller that uses a sensor to first quantify the effect of process variations on subthreshold circuits and then generates an appropriate supply voltage to overcome that effect has been proposed in [14]. De Vita and Iannaccone [15] have used a current reference circuit to design a voltage regulator providing a supply voltage that makes the propagation delay of the subthreshold digital circuits almost insensitive to temperature and process variations.…”
Section: Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…Body-biasing has also been proposed to mitigate the impact of variations [13]. A controller that uses a sensor to first quantify the effect of process variations on subthreshold circuits and then generates an appropriate supply voltage to overcome that effect has been proposed in [14]. De Vita and Iannaccone [15] have used a current reference circuit to design a voltage regulator providing a supply voltage that makes the propagation delay of the subthreshold digital circuits almost insensitive to temperature and process variations.…”
Section: Related Workmentioning
confidence: 99%
“…The total energy consumed in the E-logic circuit can be calculated as (14) where E T is the energy consumption of the E-logic circuit excluding the feedback equalizer circuit and can be calculated using (1). E leak is the leakage energy in the feedback equalizer circuit and can be calculated as I leak V DD T D−equ , where T D−equ is the total latency of the E-logic and can be written as T D−equ = t PD−equ +t s−t −equ +t c−q−equ and I leak is the leakage current overhead of the adaptive feedback equalizer circuit and can be calculated as…”
Section: Modeling Of Feedback Equalizer Circuitsmentioning
confidence: 99%