Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN

Kim, Jae-Seong; Yoshizawa, Shingo; Miyanaga, Yoshikazu

doi:10.1016/j.vlsi.2011.10.002

Cited by 5 publications

(1 citation statement)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Variable word length and soft-decision Viterbi decoder [ 12 , 13 ] which reduces power dissipation in Wireless Local Area Network (LAN) hardware is designed. This is done by considering the dynamic range of the time-varying channel coefficients and adjusting the word length of the decoder to maintain able throughput requirements and low power dissipation.…”

Section: Survey Of Existing Workmentioning

confidence: 99%

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Devi¹,

Palaniappan²

2015

The Scientific World Journal

View full text Add to dashboard Cite

Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

show abstract

Section: Survey Of Existing Workmentioning

confidence: 99%

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Devi¹,

Palaniappan²

2015

The Scientific World Journal

View full text Add to dashboard Cite

show abstract

Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding

Middya,

Hsu

2023

Integration

View full text Add to dashboard Cite

A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 4×4 MIMO-OFDM systems

Kim

Yoshizawa

Miyanaga

2012

2012 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN

Cited by 5 publications

References 17 publications

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding

A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 4×4 MIMO-OFDM systems

Contact Info

Product

Resources

About

Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN

Cited by 5 publications

References 17 publications

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding

A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 4&#x00D7;4 MIMO-OFDM systems

Contact Info

Product

Resources

About

A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 4×4 MIMO-OFDM systems