Variable voltage task scheduling for minimizing energy or minimizing power

Manzak, Ali; Chakrabarti, C.

doi:10.1109/icassp.2000.860090

Cited by 28 publications

(29 citation statements)

References 5 publications

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“…Figure 5 shows EVOLVE algorithm that calculates mode deviation vector M and returns the evolved mode. It starts by calculating speedup and slowdown probabilities of all tasks using Equations (11) and (13). Then, if no real time deadline is violated, it stochastically slows down the entire task set T. In case of deadline violation, it performs slack distribution and recovery by using the tasks in T d as starting points.…”

Section: Task Selection Heuristic For Slack Distribution/recoverymentioning

confidence: 99%

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes

Gorjiara

Bagherzadeh

Chou

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage scaling in each on-chip cores individually, many on-chip voltage regulators must be used. However, the limitations in implementation of onchip inductors can reduce the efficiency, accuracy and the number of voltage modes generated by regulators. Therefore the future voltage scheduling algorithms must be efficient, even in the presence of few voltage modes; and fast, in order to handle complex applications. Techniques proposed to date, need many fine-grained voltage modes to produce energy efficient results and their quality degrades significantly as the number of modes decreases. This paper presents a new technique called Adaptive Stochastic Gradient Voltage and Task Scheduling (ASG-VTS) that quickly generates very energy efficient results irrespective of the number of available voltage modes. The results of comparing our algorithm to the most efficient approaches (RVS and EE-GLSA) show that in the presence of only four valid modes, the ASG-VTS saves up to 26% and 33% more energy. On the other hand, other approaches require at least ten modes to reach the same level of energy saving that ASG-VTS achieves with only four modes. Therefore our algorithm can also be used to explore and minimize the number of required voltage levels in the system. Categories and Subject Descriptors

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Section: Task Selection Heuristic For Slack Distribution/recoverymentioning

confidence: 99%

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes

Gorjiara

Bagherzadeh

Chou

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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“…The power consumption is at least a quadratic function of the supply voltage (hence CPU speed) in the cased of function executed. It was shown in [1,2,3] that further energy consumption can be reduced by decreasing process frequencies during the voltage selection. Investigations of DVS processors have shown that the power consumption can be decreased by up to 10 times after using voltage scales when executing real-life applications [4].…”

Section: Introductionmentioning

confidence: 99%

A hybrid Big Bang-Big Crunch algorithm for energy optimization on heterogeneous distributed system

Kang¹,

Li²,

Wang³

et al. 2017

MATEC Web Conf.

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Abstract.A hybrid algorithm is presented for global optimization of the energy consumption rather than makespan of the system. The cost profile is optimized by extending the execution time of the tasks on dynamic voltage scalable processing elements in embedded environment with meeting the execution constraints. The modified Big Bang Big Crunch (BBBC) method improves the scheduling efficiency of the tasks by simulating one of the theories of the evolution of the universe. BBBC algorithm generates disorder data points inspired by energy dissipation procedure of the Big Bang phase, and moves those data points to a single representative data point inspired by a center of mass cost approach in the Big Crunch phase. The Logistic and Sinusoidal chaotic maps are investigated and utilized to improve the movement step of the BBBC algorithm. The proposed hybrid algorithm is tested on several benchmark data sets and its performance is compared with those of Ant Colony Optimization and HEFT strategies. The simulation experiment shows that the presented evolutionary optimization algorithm is robust and suitable for energy saving.

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“…Despite their power reduction efficiency, all these DVS approaches [Bambha et al 2001;Gruian and Kuchcinski 2001;Luo and Jha 2000] do not consider and target heterogenous distributed architectures containing power managed DVS-PEs in which the dissipated power for each task execution might vary. It was shown in [Ishihara and Yasuura 1998] and [Manzak and Chakrabarti 2000] that the variations in the average switching activity (equivalent to variations in power) influence the optimal voltage schedule and hence need to be considered during the voltage selection. However, both approaches do not target distributed systems with multiple PEs executing tasks with dependencies.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Iterative schedule optimization for voltage scalable distributed embedded systems

Schmitz

Al-Hashimi

Eles

2004

ACM Trans. Embed. Comput. Syst.

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We present an iterative schedule optimisation for multi-rate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs). To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimised supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively. Further, we address the simultaneous schedule optimisation towards timing behaviour and DVS utilisation by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyse the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.

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Variable voltage task scheduling for minimizing energy or minimizing power

Cited by 28 publications

References 5 publications

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes

A hybrid Big Bang-Big Crunch algorithm for energy optimization on heterogeneous distributed system

Iterative schedule optimization for voltage scalable distributed embedded systems

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