“…Assuming that W = L = 60 nm, t ox = 8nm, N A = 5 × 10 17 cm −3 and α G = 0.6, the previous expression predicts σ V T,0 = 85 mV, which must be viewed as a lower bound for the real V T,0 spread of a 60-nm NAND array. In fact, despite atomistic doping is one of the main variability sources for V T,0 , many other contributions exist, e.g., due to process-induced tolerances [1]. The effect of the V T,0 spread on data retention was investigated referring to a fresh device at low temperature, where the V T shift from the programmed state only comes from the FG charge loss through the tunnel oxide via direct quantummechanical tunneling, neglecting all the possible detrapping and defect-assisted charge loss processes limiting data retention after cycling.…”