Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

“…It results in a high simulation effort and difficulty for further optimization. They improve their method in (Maricau & Gielen, 2010) using response surface model to speed up the simulations, where certain numbers of random samples are still required to obtain the degraded distribution information. None of the above mentioned methods proposes an analog circuit design flow considering the joint effects of process variations and lifetime parameter degradations.…”