Validation of UML Models via a Mapping to Communicating Extended Timed Automata

Graf, Susanne; Ober, Iulian

doi:10.1007/978-3-540-24732-6_9

Cited by 35 publications

(15 citation statements)

References 27 publications

(64 reference statements)

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“…The semantic choice of a single thread per component is also similar to our choice in terms of concurrency within a concurrent unit and its service instances, which is not clear in the UML/SPT standard. Ober et al propose in [10] a model checking technique to validate UML models. The focus is on a subset of UML concepts used to define an operational view of a system.…”

Section: Related Work and Discussionmentioning

confidence: 99%

Timed-Automata Semantics and Analysis of UML/SPT Models with Concurrency

Gherbi¹,

Khendek²

2007

10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)

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UML can be effectively used for the design and analysis of real-time systems. UML profiles for real-time, like the current OMG's standard UML/SPT, enable the modeling of quantitative requirements such as time constraints as well as behavioral features such as concurrency. Because of the multitude of diagrams and their complexity, UML/SPT models face the challenging issue of consistency. In this paper we look into the behavioral consistency and particularly into concurrency-related properties of UML/SPT models. In order to do so, we formally define the UML/SPT concurrency domain model in terms of timed automata. As a straightforward application of this semantics, UML/SPT concurrent models can be validated using well-established model checking techniques and tools.

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Section: Related Work and Discussionmentioning

confidence: 99%

Timed-Automata Semantics and Analysis of UML/SPT Models with Concurrency

Gherbi¹,

Khendek²

2007

10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07)

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“…Graf et al [29,30] perform a verification of UML models by extending an existing automata-based validation framework, called IF [5], to support concurrency and communication aspects. IF supports all major UML constructs.…”

Section: Verification Of Uml Statechartsmentioning

confidence: 99%

A dynamic assertion-based verification platform for validation of UML designs

Banerjee

Ray

Dasgupta

et al. 2012

SIGSOFT Softw. Eng. Notes

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Capacity limitations continue to impede widespread adoption of formal property verification in the design validation flow of software and hardware systems. The more popular choice (at least in the hardware domain) has been dynamic property verification (DPV), which is a semi-formal approach where the formal properties are checked over simulation runs. DPV is highly scalable and can support a rich specification language. The main contribution of this paper is to build an integrated DPV platform for validation of UML-based designs. Specifically, we present (a) a language, named Action-LTL (a simple extension of Linear Temporal Logic) for writing assertions over data attributes and events of UML models, and (b) an integrated dynamic assertion-verification platform for verification of UML designs. In view of the capacity limitations of existing formal property verification tools, we believe that the methods presented in this paper are of immediate practical value to the UML design community.

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“…The analysis and verification tools cover a large spectrum of techniques and methods: (70) -interactive simulation of Live Sequence Charts (56) via the play-in/ play-out tool (73) allows editing and animation/simulation of the models, -an untimed model checker (74) supports the verification of functional properties expressed as LSC or in temporal logic, -the IF verification platform (68,69) takes care of the timed verification and of schedulability analysis on the basis of a model given as extended real-time automata -theorem proving techniques that build on the interactive theorem prover PVS (75) are used in order to reason about properties of unbounded systems (e.g., unbounded size, or unbounded message queues). (76,77) …”

Section: A Uml Verification Platform For Embedded Systemsmentioning

confidence: 99%

Dynamic and Formal Verification of Embedded Systems: A Comparative Survey

Loghi

Margaria

Pravadelli

et al. 2005

Int J Parallel Prog

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Embedded Systems, by their nature, constitute a meeting point for communities with extremely different background. In particular, the high demands for quality and reliability for embedded systems have led to complementary quality assurance efforts: hardware engineers have developed techniques for dynamic verification in terms of co-simulation, which, in particular, addresses the different nature of hardware and software components. Thus these techniques are tailored for the transactional level, which comprises dedicated models for the hardware and the software parts. On the other hand, there is a bulk of work on formal verification techniques, which typically address higher levels of abstraction. These techniques are exhaustive in the sense that they cover all the infinite possible paths of their models, however at the price of neglecting many of the low-level aspects treated by co-simulation. It is the goal of this paper to increase the mutual understanding between these communities and to animate research at this exciting borderline.

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Validation of UML Models via a Mapping to Communicating Extended Timed Automata

Cited by 35 publications

References 27 publications

Timed-Automata Semantics and Analysis of UML/SPT Models with Concurrency

Timed-Automata Semantics and Analysis of UML/SPT Models with Concurrency

A dynamic assertion-based verification platform for validation of UML designs

Dynamic and Formal Verification of Embedded Systems: A Comparative Survey

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