V-Shaped InAs/Al0.5Ga0.5Sb Vertical Tunnel FET on GaAs (001) Substrate With I $_{\text {ON}}=\text {433}\,\,\mu$ A. $\mu$ m $^{-\text {1}}$ at V $_{\text {DS}}= \text {0.5}$ V

In-plane InGaAs/Ga(As)Sb nanowire based tunnel junctions grown by selective area molecular beam epitaxy

“…A quantitative analysis of the composition of the alloys in those different areas is proposed in figure 9. It confirms the previous observation with an As/(As +Sb) ratio of about 58%-59% in the GaAsSb deposited on top of InGaAs for both orientation and larger than 63% on side facets for [1][2][3][4][5][6][7][8][9][10] NWs whereas a composition close to the InP lattice matched alloy (GaAs 0,49 Sb 0,51 ) is measured for the material deposited on the (111) facets of [110]-oriented NWs. In the angles, the As content reaches up to 68% for this direction.…”

“…The reduced cross-section of the tunneling interface required to manage a good electrostatic control of the tunneling current or to reduce the junction capacitance can be achieved with an aggressive top down etching of a two dimensional epitaxial layer. Even though very small dimensions can be achieved, trap assisted tunneling related to surface states on etched mesa side walls cannot be avoided with this strategy [4]. Bottom-up approach based on gold assisted vapor liquid solid (VLS) grown vertical nanowires is a good alternative to avoid etching [5] but the achievement of abrupt interfaces with a good control of ternary alloy composition is quite tricky due to the accumulation of III-elements in the catalyst.…”

Investigation Influence of Channel Transport on Output Characteristics in Sub-100nm Heterojunction Tunnel FET

“…Although there are two transport processes in TFETs: band-to-band tunneling (BTBT) at the tunneling junction and the subsequent channel transport along the channel, the influence of the latter is often concealed due to the drawback of low On-state current. However, with the developments of fabrication process, the encouraging results, such as SS of 48mV/decade combined with I 60 (the current at which the SS is equal to 60mV/decade) of 0.31μA/μm, and high On-current of 433μA/μm at 0.5V of drain bias, have been experimentally reported in III-V heterojunction TFET (H-TFET) [5], [6], and the channel length in H-TFETs are also scaling down to sub-100nm [5], [7]. At this time, how the channel transport influences the performance of H-TFETs toward state-of-the-art should be investigated in details for their industrial design and implementation in circuit.…”

An analytical drain current model for graphene nanoribbon tunnel field-effect transistors

“…1,2) The ON-state current of the silicon-based TFET, however, is very small and the I on /I off ratio is low, owing to the large energy band gap of silicon. TFET-based on III-V materials, such as InAs or InSb, [3][4][5][6][7][8] the energy band gap and the carrier's mobility can be improved, but because of the mismatch between the crystal materials, there are a lot of traps at the interface, and the subthreshold swing of the device deteriorates (>90 mV dec −1 ).…”