Utilizing surplus timing for power reduction

Hamada, Mototsugu; Ootaguro, Y.; Kuroda, Tadahiro

doi:10.1109/cicc.2001.929730

Cited by 62 publications

(38 citation statements)

References 3 publications

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“…An often used low voltage V L is 70% of the high voltage V H . 6,13,28,31,37 However, some authors 9,28,43 suggest that the optimal value of V L for minimizing total power is 50% of V H . Authors in 51 assume that all gates initially have the lowest possible V L .…”

Section: Background and Motivationmentioning

confidence: 99%

“…Published work also reports rules of thumb 13 for optimum voltage ratios in multiple-V DD circuits. Thus, for…”

Section: Background and Motivationmentioning

confidence: 99%

“…The authors claim 13 that these rules of thumb give supply voltages, which reduce power to within 1% of the theoretical minimum for an assumed triangle shaped path delay distribution. These results show that the power savings tend to saturate as the number of supplies is increased and also that the savings decrease as the supply voltage is scaled and when V th /V H is higher.…”

Section: Background and Motivationmentioning

confidence: 99%

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Energy-Efficient Dual-Voltage Design Using Topological Constraints

Allani¹,

Agrawal

2013

Journal of Low Power Electronics

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We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a circuit and its nominal single supply voltage, we find a suitable value for a lower second supply voltage that is likely to give the best advantage in power reduction. Besides, using the critical path timing constraint and a linear-time gate slack calculation we also classify gates into three groups. All gates in Group 1 can be simultaneously assigned the lower voltage. Any gate in Group 2 can be assigned the lower voltage but then gate slacks must be recalculated because the group classifications may change. No gate in Group 3 can be assigned the lower voltage. A second step then assigns the lower voltage to the largest possible number of gates using the gate classifications and imposing a topological constraint, preventing any low voltage gate from feeding into a higher voltage gate, thus avoiding the use of level converters. SPICE simulation of dual-voltage ISCAS'85 benchmark circuits using the 90nm bulk CMOS PTM (predictive technology model) shows energy savings of up to 60% with no increase in the original critical path delay and up to 70% with relaxed critical path delay.

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Section: Background and Motivationmentioning

confidence: 99%

“…Published work also reports rules of thumb 13 for optimum voltage ratios in multiple-V DD circuits. Thus, for…”

Section: Background and Motivationmentioning

confidence: 99%

Section: Background and Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Energy-Efficient Dual-Voltage Design Using Topological Constraints

Allani¹,

Agrawal

2013

Journal of Low Power Electronics

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“…Previous works [2] [3] have shown that using two supply and threshold voltages provides substantial improvement in power dissipation and the use of additional voltages results in small power improvements which is hard to justify the additional costs associated with multiple supply and threshold voltages. Dual-Vdd designs have shown significant improvements in power dissipation in the range of 40-50% [3,4], but these improvements have been expected to decrease with process scaling [5]. Reference [2] shows that an additional threshold voltage can be used to maintain the power reduction with scaling dimensions.…”

Section: Introductionmentioning

confidence: 99%

Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment

Srivastava

Sylvester

Blaauw

2004

Proceedings of the 41st Annual Design Automation Conference

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We develop an approach to minimize total power in a dual-Vdd and dual-Vth design. The algorithm runs in two distinct phases. The first phase relies on upsizing to create slack and maximize low Vdd assignments in a backward topological manner. The second phase proceeds in a forward topological fashion and both sizes and re-assigns gates to high Vdd to enable significant static power savings through high Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS and dual-Vth/sizing algorithms demonstrate the advantage of the algorithm over a range of activity factors, including an average power reduction of 30% (50%) at high (nominal) primary input activities.

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“…Hamada et al derived a set of practical expressions for optimal number and values of discrete supplies, thresholds, and gate sizes. They concluded that no more than three discrete values are needed for each tuning variable [15]. Their analysis was, however, limited to single-variable optimizations.…”

Section: Power Minimizationmentioning

confidence: 99%

Methods for true power minimization

Brodersen

Horowitz

Marković

et al.

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

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MotivationDuring the past few years the nature of integrated circuit design has slowly changed; the continued scaling of the underlying technology has moved designs from being limited by the amount of functionality on a chip, to being powerconstrained. The nature of the power constraints may be different (i.e., the chips in cell phones vs. desktop processors), but in many cases today, and in most cases in the future, the performance one can achieve will depend on the how efficiently that computation can be done per unit of energy. While historically for CMOS circuits there has always been a strong relationship between power and performance, the power of the chip remained within the allowable power envelope; in this scenario, designers focused primarily on achieving the needed performance. Power, if considered, was only checked to ensure that it was not too high. In order to achieve the highest performance in the power-limited scaling regime, one must use the most energy efficient method available, otherwise one will overrun the specified power/energy budget.This new relationship between peak achievable performance and energy efficiency changes the way one tends to think about design. Traditionally, architects try to create a machine organization that has the "best" performance. This design is then passed to the block designers, who again try to build the blocks in order to achieve the peak performance. If energy efficiency is the key in achieving high performance, optimizing each layer individually will not lead to an optimal design, rather, it will lead to a design that dissipates too much power. Instead, one needs to optimize the design by using techniques that are the most power efficient first, until the desired performance or power is reached.Merely optimizing for the most energy efficient design is misleading, since this approach rarely achieves needed performance. Thus, the correct optimization typically either minimizes the energy consumption, subject to a throughput constraint, or maximizes the amount of computation for a given amount of energy. Both these design optimizations can be achieved if the tradeoffs between the energy and delay are known.The dramatic increase in leakage currents in today's (and future) technologies adds another factor to the optimization problem. Since some of the leakage power can be traded off for the dynamic power of the design, the optimization needs to select the correct balance here, as well. Furthermore, as the ratio of leakage-to-active power increases, the optimal architecture and circuits also change. From a power budget perspective, leaky gates are expensive since they cost watts when they are inactive. Thus, for leaky technologies, one wants to keep the gates as active as possible, leading to deeply pipelined, rather than parallel, architectures.Design methods that explore "true power minimization" need to work in a large dimension search space, where power and performance of different solutions are compared. This includes system architecture optimization ...

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Utilizing surplus timing for power reduction

Cited by 62 publications

References 3 publications

Energy-Efficient Dual-Voltage Design Using Topological Constraints

Energy-Efficient Dual-Voltage Design Using Topological Constraints

Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment

Methods for true power minimization

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