Using value prediction to increase the power of speculative execution hardware

Gabbay, Freddy; Mendelson, Avi

doi:10.1145/290409.290411

Cited by 58 publications

(44 citation statements)

References 14 publications

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“…We adopt some frequently-used and easy-to-implement prediction strategies to detect likely timing errors [9,27,29,38]. These predictors apply the principle of temporal locality for timing errors.…”

Section: Prediction Strategiesmentioning

confidence: 99%

Identifying and predicting timing-critical instructions to boost timing speculation

Xin¹,

Joseph²

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins and eliminating power/performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions. In this paper, we analyze gatelevel hardware models for an execution pipeline and demonstrate pronounced locality in instruction-level error rates due to value locality and data dependences. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and error padding techniques to avoid the full recovery cost of timing errors. We show that with simple prediction strategies our mechanism can reduce 80% of the performance penalty incurred by error recovery on average. This allows us to alleviate some limitations of timing speculation and improves energy-efficiency by 21% when compared to baseline timing speculation techniques using the same dynamic adaptive tuning mechanism.

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Section: Prediction Strategiesmentioning

confidence: 99%

Identifying and predicting timing-critical instructions to boost timing speculation

Xin¹,

Joseph²

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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“…p), or the status of the lock in the case of a locking construct (with do e), is "guessed", or "predicted" -as regards loads from the memory, this is known as value prediction, and was introduced in [11,19]. These guessed values may be written by other threads, which are ignored at this stage.…”

Section: For Any Expression E Of the Run-time Language Either E Ismentioning

confidence: 99%

“…We adopt and extend the approach presented in [7], that is, we define, using a pretty standard operational style, the speculative semantics of an expressive language, namely a call-by-value λ-calculus with mutable state and threads. Our formalization relies on extending the usual notion of an evaluation context [9], and using value prediction [11,19] as regards the values read from the memory. By introducing speculation contexts, we are able to formalize out of order executions, as in relaxed memory models, and also branch prediction [26], allowing to compute in the alternatives of a conditional branching construct.…”

Section: Introductionmentioning

confidence: 99%

A Theory of Speculative Computation

Boudol

Petri

2010

Programming Languages and Systems

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Abstract. We propose a formal definition for (valid) speculative computations, which is independent of any implementation technique. By speculative computations we mean optimization mechanisms that rely on relaxing the flow of execution in a given program, and on guessing the values read from pointers in the memory. Our framework for formalizing these computations is the standard operational one that is used to describe the semantics of programming languages. In particular, we introduce speculation contexts, that generalize classical evaluation contexts, and allow us to deal with out of order computations. Regarding concurrent programs, we show that the standard DRF guarantee, asserting that data race free programs are correctly implemented in a relaxed semantics, fails with speculative computations, but that a similar guarantee holds for programs that are free of data races in the speculative semantics.

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“…Another approach in speculative schemes is to predict the values that will result from an operation, usually a load (e.g, [2]). This allows execution to continue without waiting for the result of the instruction, at the cost of more changes to roll back in the case of a misprediction.…”

Section: Out-of-order and Superscalarmentioning

confidence: 99%

“…1.000000 xi (1,3) 1.000000 xi (1,4) 1.000000 xi (1,5) 1.000000 xi (2,6) 1.000000 xi (3,6) 1.000000 xi(0,0)…”

Section: B3 Optimal Integer Linear Programming Solution 183mentioning

confidence: 99%

Adding limited reconfigurability to superscalar processors

Epalza

Ienne²,

Mlynek

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.

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For the last thirty years, electronics, at first built with discrete components, and then as Integrated Circuits (IC), have brought diverse and lasting improvements to our quality of life. Examples might include digital calculators, automotive and airplane control assistance, almost all electrical household appliances, and the almost ubiquitous Personal Computer. ApplicationSpecific Integrated Circuits (ASICs) were traditionally used for their high performance and low manufacturing cost, and were designed specifically for a single application with large volumes. But as lower product lifetimes and the pressures of fast marketing increased, ASICs' high design cost pushed for their replacement by Microprocessors. These processors, capable of implementing any functionality through a change in software, are thus often called General Purpose Processors.General purpose processors are used for everyday computing tasks, and found in all personal computers. They are also often used as building blocks for scientific supercomputers. Superscalar processors such as these require ever more processing power to run complex simulations, video games or versatile telecoms services. In the case of embedded applications, e.g. for portable devices, both performance and power consumption must be taken into account.In a bid to adapt a processor to some extent to select applications, fully reconfigurable logic can greatly improve the performance of a processor, since it is shaped for the best possible execution with the available resources. However, as reconfigurable logic is far slower than custom logic, this gain is possible only for some specific applications with large parallelism, after a detailed study of the algorithm. Even though this process can be automated, it still requires large computing resources, and cannot be performed at run time.To reduce the loss in speed compared to custom logic, it is possible to limit the reconfigurability to increase the breadth of applications where performance can be improved. However, as the application space increases, a careful analysis and design of the reconfigurability is required to minimize the speed loss, notably when dynamic reconfiguration is considered.iii iv As a case study, we analyze the feasibility of adding limited reconfigurability to the Floating Point Units (FPUs) of a general purpose processor. These rather large units execute all floating point operations, and may also be used for integer multiplication. If an application contains few or infrequent instructions that must be executed by the FPU, this idle hardware only increases power consumption without enhancing performance. This is often the case in non-scientific applications and even many recent and detailed video games which make heavy use of hardware display accelerators for 3D graphics.In a fast multiplier such as can be found in the FPU of a high performance processor, the logic to perform multiplication is a large tree of compressors to add all the partial products together. It is possible to add logic to a...

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Using value prediction to increase the power of speculative execution hardware

Cited by 58 publications

References 14 publications

Identifying and predicting timing-critical instructions to boost timing speculation

Identifying and predicting timing-critical instructions to boost timing speculation

A Theory of Speculative Computation

Adding limited reconfigurability to superscalar processors

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