Using the weak inversion region to optimize input stage design of CMOS op amps

Comer, Douglas E.

doi:10.1109/tcsii.2003.821517

Cited by 93 publications

(36 citation statements)

References 11 publications

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“…where I D0 is the technology dependent sub-threshold current obtained for V GS = V th , where V GS is the gate-source voltage and V th is the threshold voltage, v t is the thermal voltage, W/L is the aspect ratio and n is the sub-threshold factor [27]. For V GS = V th , equation 3 can be further simplified as:…”

Section: Analog Power Consumptionmentioning

confidence: 99%

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Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Bhattacharyya

Gruenwald

Jansen

et al. 2018

JLPEA

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Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 µm CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 µW. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD).

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Section: Analog Power Consumptionmentioning

confidence: 99%

“…A vivid description about sub-threshold operation is provided in [27][28][29]. For the design of the analog part, weak-inversion region of operation is used extensively which is discussed in detail for some of the circuits.…”

Section: Analog Power Consumptionmentioning

confidence: 99%

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Bhattacharyya

Gruenwald

Jansen

et al. 2018

JLPEA

View full text Add to dashboard Cite

show abstract

“…In addition, the transistors are biased in the weak or moderate inversion regions as such a biasing provides relevant advantages for high-gain/low-frequency applications compared to the strong inversion region [20]. However, one of the main drawback is that the slew rate decreases slightly in these regions [21]. Considering the design of the CPA, the drain current I D of the input transistor affects both the CPA noise and GBW.…”

Section: Ps Max Smentioning

confidence: 99%

Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

et al. 2014

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A low power analog front-end circuit for silicon (Si) detectors has been fabricated in 0.35 µm CMOS technology. It has been designed to read out signals from large-capacitance Si detectors for incident electron energy ranging from 50 keV to 725 keV. In order to quantify electron energy, the front-end integrates a charge preamplifier, a pulse shaper, a peak detector and an event-driven analog-to-digital converter (ADC). The complete front end including the ADC dissipates 2.5 mW for a maximum electron detecting rate of 650 kHz. The charge-to-voltage gain is approximately 60 mV/fC for a charge range of 0.6 fF to 32 fF. The measured equivalent noise charge (ENC) is 3119 e − for a 40 pF detector parasitic capacitance. Index TermsSi Detector, Charge preamplifier, electron energy measurement.

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“…MOS transistors operating in the subthreshold region can be used to design low-power low-voltage op amps [24]. In order to allow a transistor to operate in the subthreshold region, a constraint for strong inversion operation should not be imposed on the transistor.…”

Section: Subthreshold Region Designmentioning

confidence: 99%

Design of CMOS Op Amps Using Adaptive Modeling of Transistor Parameters

Yu¹

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A design paradigm using sequential geometric programming is presented to accurately design CMOS op amps with BSIM3. It is based on new adaptive modeling of transistor parameters through the operating point simulation. This has low modeling cost as well as great simplicity and high accuracy. The short-channel dc, high-frequency small-signal, and short-channel noise models are used to characterize the physical behavior of submicron devices. For low-power and low-voltage design, this paradigm is extended to op amps operating in the subthreshold region. Since the biasing and modeling errors are less than 0.25%, the characteristics of the op amps well match simulation results. In addition, small dependency of design results on initial values indicates that a designed op amp may be close to the global optimum. Finally, the design paradigm is illustrated by optimizing CMOS op amps with accurate transfer function.Index Terms-CMOS op amp design, subthreshold region design, sequential geometric programming, adaptive transistor parameter modeling, shortchannel weak inversion noise model

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Using the weak inversion region to optimize input stage design of CMOS op amps

Cited by 93 publications

References 11 publications

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

Design of CMOS Op Amps Using Adaptive Modeling of Transistor Parameters

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