Using the SimOS machine simulator to study complex computer systems

Rosenblum, Mendel; Bugnion, Edouard; Devine, Scott; Herrod, Stephen Alan

doi:10.1145/244804.244807

Cited by 249 publications

(128 citation statements)

References 5 publications

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“…High-level simulators are commonly used in the domain of embedded systems e.g. [21], [24], [27]. However, these type of simulators are rarely used in generalpurpose multi-or many-core systems.…”

Section: Related Workmentioning

confidence: 99%

High-level simulation of concurrency operations in microthreaded many-core architectures

Uddin¹

2015

GSTF J Comput

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Abstract-Computer architects are always interested in analyzing the complex interactions amongst the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate simulation of the execution time is used. However, the cycleaccurate simulator can execute at the rate of 100K instructions per second, divided over the number of simulated cores. This means that the evaluation of a complex application with complex concurrency interactions on contemporary multi-core machine can be very slow. To perform efficient design space exploration we present a co-simulation environment, where the detailed execution of concurrency instructions in the pipeline of microthreaded cores and the interactions amongst the hardware components are abstracted. We present the evaluation of the high-level simulation framework against the cycle-accurate simulation framework. The results show that high-level simulator is faster and less complicated than cycle-accurate simulator and has reasonable accuracy.

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Section: Related Workmentioning

confidence: 99%

High-level simulation of concurrency operations in microthreaded many-core architectures

Uddin¹

2015

GSTF J Comput

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“…Simulation toolsets commonly used in academia include: SimpleScalar [4], IMPACT [9], and SimOS [28].…”

Section: Heuristic Approaches For Performance Modeling and Measurementmentioning

confidence: 99%

Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures

Padmanabhan

Jones

Schuehler

et al. 2005

Int J Parallel Prog

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We describe our experience using reconfigurable architectures to develop an understanding of an application's performance and to enhance its performance with respect to customized, constrained logic. We begin with a standard ISA currently in use for embedded systems. We modify its core to measure performance characteristics, obtaining a system that provides cycle-accurate timings and presents results in the style of gprof, but with absolutely no software overhead. We then provide cache-behavior statistics that are typically unavailable in a generic processor. In contrast with simulation, our approach executes the program at full speed and delivers statistics based on the actual behavior of the cache subsystem. Finally, in response to the performance profile developed on our platform, we evaluate various uses of the FPGA-realized instruction and data caches in terms of the application's performance.

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“…Simulation toolsets commonly used in academia include: SimpleScalar [4], IMPACT [7], and SimOS [21]. Given the long runtimes associated with simulation modeling, it is a common practice to limit the simulation execution to only a single application run, not including the OS and its associated performance impact.…”

Section: Introduction and Related Workmentioning

confidence: 99%