Using the first-level cache stack distance histograms to predict multi-level LRU cache misses

Ji, Kecheng; Ling, Ming; Shi, Longxing

doi:10.1016/j.micpro.2017.10.001

Cited by 11 publications

(5 citation statements)

References 13 publications

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“…The second category focused on those models of hierarchal memory systems in a single processor. Ji et al 9 , 10 created an analytical model to estimate the cache misses' ratios using the level one cache stack distance histogram. In 11 , another analytical model was introduced to estimate the level two cache behavior based on the effect of cache inclusion/exclusion policies.…”

Section: Background and Motivationmentioning

confidence: 99%

Performance aware shared memory hierarchy model for multicore processors

Mohamed

Mubark

Zagloul

2023

Sci Rep

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Despite the fact that multicore processors have a better instruction execution speed and lower power consumption, they also encounter a set of design challenges. The appearance of multicore and many core architectures has raised the problem of managing shared hierarchical memory systems. The main focus of this paper is to evaluate the behavior of shared hierarchical memory systems by modeling their response time analytically. Since the gap between the memory and processor speed increases rapidly, it gets more crucial to find an analytical model that includes the significant factors that affect the performance of hierarchical memory systems. The proposed model considers the interdependence between different memory layers and differentiates between the memory response time and memory system time. Moreover, the model evaluates the effect of memory hierarchy on the variance of the memory access time. The existence of a large variance can lead to extremely long wait queues which can dramatically affect the performance of multicore processors

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Section: Background and Motivationmentioning

confidence: 99%

Performance aware shared memory hierarchy model for multicore processors

Mohamed

Mubark

Zagloul

2023

Sci Rep

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“…M Ling and J Ge [6] [7] proposed the RST table and Hit-RDH, which describe more detailed information of the software traces, as the inputs to model the L2 cache RDH. K Ji et al [12] [13] used the L1 cache SDH to predict the downstream cache misses by constructing a total probability formula set. Jasmine Madonna S et al [14] put forward an analytical model to calculate the L2 cache miss rate based on the analysis of the influence of cache inclusion policies.…”

Section: Related Workmentioning

confidence: 99%

“…Eq. (12) gives the way to calculate the 𝑀𝑀𝑅𝑅𝐴𝐴𝐻𝐻(𝑎𝑎). In this equation, 𝑅𝑅𝐴𝐴𝐻𝐻′(𝑎𝑎) is predicted in Step 1 of Fig.…”

Section: B Quantifying the Split Effectmentioning

confidence: 99%

“…If the stack distance is no less than associativity, which indicates a cache miss, we accumulate 1 on the corresponding memory address in AAD. To make a trade off between space/time overheads and accuracies, we choose to cut of the profiled L1 reuse/stack distances at 1024 and accumulate the number of references with larger reuse distances to the reuse distance bar of 1024, which is also applied in the work of [11,12,13,16]. The RST, Hit-RDH and AAD updating procedures are just attached to the progress of RDH and SDH profiling.…”

Section: Integrating With the Upstream Cache Modelmentioning

confidence: 99%

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Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Ling

Wang

et al. 2021

IEEE Access

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To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely used in modern processors. However, the complexity of the architectures makes the modeling of shared caches extremely complex. In this paper, we propose a data-sharing aware analytical model for estimating the miss rates of the downstream shared cache in a multi-core environment. Moreover, the proposed model can also be integrated with upstream cache analytical models with the consideration of multi-core private cache coherent effects. The integration avoids time-consuming full simulations of the cache architecture, which are required by conventional approaches. We validate our analytical model against gem5 simulation results under 13 applications from PARSEC 2.1 benchmark suites. We compare the L2 cache miss rates with the results from gem5 under 8 hardware configurations including dual-core and quad-core architectures. The average absolute error is less than 2% for all configurations. After integrated with the upstream model, the overall average absolute error is 8.03% in 4 hardware configurations. As an application case of the integrated model, we also evaluate the miss rates of 57 different cache configurations in multi-core and multi-level cache scenarios.

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“…The second part is for the models for multi-level cache architectures. K Ji et al [9] [10] used the L1 cache SDH to predict the multi-level cache misses based on a total probability formula. It considers all the possible situations of distance distributions in a reuse epoch, which makes the complexity of the algorithm extremely high.…”

Section: Related Workmentioning

confidence: 99%

Fast modeling L2 cache reuse distance histograms using combined locality information from software traces

Ling

Wang

2020

Journal of Systems Architecture

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To mitigate the performance gap between the CPU and the main memory, multi-level cache architectures are widely used in modern processors. Therefore, modeling the behaviors of the downstream caches becomes a critical part of the processor performance evaluation in the early stage of Design Space Exploration (DSE). In this paper, we propose a fast and accurate L2 cache reuse distance histogram model, which can be used to predict the behaviors of the multi-level cache architectures where the L1 cache uses the LRU replacement policy and the L2 cache uses LRU/Random replacement policies. We use the L1 reuse distance histogram and two newly proposed metrics, namely the RST table and the Hit-RDH, that describing more detailed information of the software traces as the inputs. The output of our model is the L2 cache reuse distance histogram, based on which the L2 cache miss rates can be evaluated. We compare the L2 cache miss rates with the results from gem5 cycle-accurate simulations of 15 benchmarks chosen from SPEC2006. The average absolute error is less than 5%, while the evaluation time can be sped up by 7.38 times. We also extend our model into a multi-core architecture in which two cores share a unified L2 cache. The error of our model in this case is less than 7%.

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Using the first-level cache stack distance histograms to predict multi-level LRU cache misses

Cited by 11 publications

References 13 publications

Performance aware shared memory hierarchy model for multicore processors

Performance aware shared memory hierarchy model for multicore processors

Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Fast modeling L2 cache reuse distance histograms using combined locality information from software traces

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