Using Synchronization Stalls in Power-aware Accelerators

Jooya, Ali; Baniasadi, Amirali

doi:10.7873/date.2013.091

Cited by 1 publication

(2 citation statements)

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“…In the deep-submicron era, the contribution of the static power to total power consumption is significantly increasing [49,87]. Therefore, several techniques for reducing static power consumption have been proposed over the past few years [1,2,7,28,33,37,41,42,46,58,60,61,73,80,91,93,95,105,107]. In this section, we briefly explain power-Gating and voltage-scaling, two widely used techniques shown to be effective at reducing static power.…”

Section: Static Power Reduction Techniquesmentioning

confidence: 99%

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Itap

Sadrosadati

Ehsani

Falahati³

et al. 2019

ACM Trans. Archit. Code Optim.

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Graphics Processing Units (GPUs) are widely used as the accelerator of choice for applications with massively data-parallel tasks. However, recent studies show that GPUs suffer heavily from resource underutilization, which, combined with their large static power consumption, imposes a significant power overhead. One of the most power-hungry components of a GPU-the execution units-frequently experience idleness when (1) an underutilized warp is issued to the execution units, leading to partial lane idleness, and (2) there is no active warp to be issued for the execution due to warp stalls (e.g., waiting for memory access and synchronization). Although large in total, the idle time of execution units actually comes from short but frequent stalls, leaving little potential for common power saving techniques, such as power-gating. In this article, we propose ITAP, a novel idle-time-aware power management technique, which aims to effectively reduce the static energy consumption of GPU execution units. By taking advantage of different power management techniques (i.e., power-gating and different levels of voltage scaling), ITAP employs three static power reduction modes with different overheads and capabilities of static power reduction. ITAP estimates the idle period length of execution units using prediction and peek-ahead techniques in a synergistic way and then applies the most appropriate static power reduction mode based on the estimated idle period M. Sadrosadati performed part of this work at ETH Zürich. L. Orosa was supported by FAPESP fellowship 2016/18929-4.

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Section: Static Power Reduction Techniquesmentioning

confidence: 99%

“…GPU PG. Several works attempt to power-gate idle execution lanes [7,33,41,42,46]. Warped Gates [2] aims to improve the energy efficiency of GPUs by leveraging the fact that integer and floating-point instructions cannot be executed simultaneously.…”

Section: Related Workmentioning

confidence: 99%