Using source-to-source compilation to instrument circuits for debug with High Level Synthesis

Monson, Joshua S.; Hutchings, Brad

doi:10.1109/fpt.2015.7393129

Cited by 8 publications

(8 citation statements)

References 18 publications

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“…3) An evaluation and a validation of the proposed framework on a set of OpenCL benchmarks are performed. On the reported benchmarks, the average logic resource requirement is between 1.5 and 6 times lower than those reported in best previously published works [23] [24] [25].…”

Section: Introductionmentioning

confidence: 57%

“…Table 6 compares the logic resource overhead per instrument of our framework to those of previous works. The logic area overhead shows that our framework consumes on average 6 times fewer FFs and almost 1.5 times fewer ALUTs than the best previously published work [23] in terms of logic overhead when one instrument is inserted. For example, the average relative Flip-Flop utilization overhead (compared to the original design) in our experiments is 0.10 %, which can be compared to the value of 0.6 % in [23], while the average logic element (LE(LU)) utilization is 2.5% in [25].…”

Section: Framework Comparisonmentioning

confidence: 84%

“…The logic area overhead shows that our framework consumes on average 6 times fewer FFs and almost 1.5 times fewer ALUTs than the best previously published work [23] in terms of logic overhead when one instrument is inserted. For example, the average relative Flip-Flop utilization overhead (compared to the original design) in our experiments is 0.10 %, which can be compared to the value of 0.6 % in [23], while the average logic element (LE(LU)) utilization is 2.5% in [25]. To the best of our knowledge, our proposed framework is also the first that can simultaneously support, debugging and timing performance analysis capabilities for OpenCL-based FPGA designs at FPGA clock cycle accuracy, as summarized in Table 7.…”

Section: Framework Comparisonmentioning

confidence: 84%

“…Monson and Hutchings [40], [23] used a source-to-source compilation approach to enhance observability, focusing on the C code rather than the RTL code generated by HLS tools. The source-to-source approach consists of adding debugging ports that are connected to C expressions in the source code, and these can provide access points in the design.…”

Section: Related Work On In-system Fpga Instrumentationmentioning

confidence: 99%

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In-FPGA Instrumentation Framework for OpenCL-Based Designs

2020

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The productivity achieved when developing applications on high-performance reconfigurable heterogeneous computing (HPRHC) systems is increased by using the Open Computing Language (OpenCL). However, the hardware produced by OpenCL compilers in field-programmable gate arrays (FPGAs) can result in severe performance bottlenecks that are challenging to solve. The problem is compounded by the fact that the generated netlist details are disorganized, making them mostly unreadable and only partially visible to designers. This paper proposes an in-FPGA instrumentation method and a new framework for extracting the FPGA-cycle-accurate timing performances of OpenCL-based designs. The results clearly show that the chosen execution model for OpenCL-based designs strongly affects the timing performance when it is not properly implemented. Our framework is implemented on an HPRHC platform that contains a CPU and two Arria10 FPGAs, and it is evaluated with a wide variety of benchmarks with different complexities. After testing on the reported benchmarks, the average logic overhead for one inserted instrument is 0.2 % of the total amount of adaptive look-up tables (ALUTs) and 0.1 % of the total registers in an FPGA. This resource utilization is between 1.5 and six times lower than those reported in the best previously published works. The scalability of the framework is also evaluated by inserting up to 50 instruments. The experimental results show that the average logic utilization per instrument is 0.19 % of the ALUTs and 0.17 % of the registers in the FPGA when 50 instruments are inserted.

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Section: Introductionmentioning

confidence: 57%

Section: Framework Comparisonmentioning

confidence: 84%

Section: Framework Comparisonmentioning

confidence: 84%

Section: Related Work On In-system Fpga Instrumentationmentioning

confidence: 99%

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In-FPGA Instrumentation Framework for OpenCL-Based Designs

2020

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“…RELATED WORK overall productivity. Some other works [43,45,97] also target using trace buffers to record the insitu of HLS-generated designs, but provide different features to enhance the visibility of design. For example, Monson [43] proposes the use of Event Observability Port (EOP), which is essentially a top-level RTL port that corresponds to the output of a specific expression in the original source, to provide observability of source-level events from the corresponding HLS-generated hardware.…”

Section: Execution-based Discrepancymentioning

confidence: 99%

Improving the productivity of high-level synthesis by advancing reuseability and verifiability

Yang¹

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for the kind support and advice. I would like to thank all the great people I work with in Advanced Digital Sciences Center, Singapore. I would like to thank Prof. Deming Chen for taking me into this world-class research team to pursue valuable research goals. I would like to thank all the teammates, Swathi Gurumani, Hongbin Zheng, Nguyen Quoc Duy Tan and Augustine Koh for their kind help and the fruitful collaboration. Meanwhile, I would like to thank all my past and present friends and colleagues in the Hardware and Embedded Systems Lab in Nanyang Technological University for making our days in Singapore much more interesting.Finally, with all of my heart, I wish to express my eternal gratitude to my family for their everlasting encouragement, consolation, understanding and selfless devotion. I want to thank my parents, Wang Mingying (王明瑛) and Yang Shunhe (杨顺和), for your endless love throughout my whole life and the huge support that backs me up when I cannot physically take care of Wanxin and Shaxi. You are the source of everything I become. I would like to thank my wife, Wang Wanxin (王万新), for sharing your whole life and faith with me, and bringing our baby to this world with all you have. It is my greatest blessing to have you as my beloved. I would like to thank my daughter, Yang Shaxi (杨沙溪), for coming into my life as the greatest gift ever and opening a new era of my life.

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Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilation

Monson¹,

Hutchings

2018

Journal of Parallel and Distributed Computing

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Using source-to-source compilation to instrument circuits for debug with High Level Synthesis

Cited by 8 publications

References 18 publications

In-FPGA Instrumentation Framework for OpenCL-Based Designs

In-FPGA Instrumentation Framework for OpenCL-Based Designs

Improving the productivity of high-level synthesis by advancing reuseability and verifiability

Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilation

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